Place & Route TRACE Report

Loading design for application trce from file kurs17_impl1.ncd.
Design name: top
NCD version: 3.3
Vendor:      LATTICE
Device:      LCMXO2-1200HC
Package:     TQFP100
Performance: 5
Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status:                     Final          Version 1.44.
Performance Hardware Data Status:   Final          Version 34.4.
Setup and Hold Report

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Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
Sat Sep 23 19:43:24 2023

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
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Command line:    trce -v 10 -gt -sethld -sp 5 -sphld m -o Kurs17_impl1.twr -gui Kurs17_impl1.ncd Kurs17_impl1.prf 
Design file:     kurs17_impl1.ncd
Preference file: kurs17_impl1.prf
Device,speed:    LCMXO2-1200HC,5
Report level:    verbose report, limited to 10 items per preference
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Preference Summary

  • FREQUENCY NET "Clock" 14.000000 MHz (0 errors)
  • 4096 items scored, 0 timing errors detected. Report: 90.179MHz is the maximum frequency for this preference. BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY NET "Clock" 14.000000 MHz ; 4096 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 60.340ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q MelodyPlayer_inst/Duration_ms_i12 (from Clock +) Destination: FF Data in MelodyPlayer_inst/HalfPeriod_us_i13 (to Clock +) FF MelodyPlayer_inst/HalfPeriod_us_i12 Delay: 10.840ns (24.6% logic, 75.4% route), 6 logic levels. Constraint Details: 10.840ns physical path delay MelodyPlayer_inst/SLICE_52 to MelodyPlayer_inst/SLICE_158 meets 71.429ns delay constraint less 0.000ns skew and 0.249ns CE_SET requirement (totaling 71.180ns) by 60.340ns Physical Path Details: Data path MelodyPlayer_inst/SLICE_52 to MelodyPlayer_inst/SLICE_158: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R7C8B.CLK to R7C8B.Q0 MelodyPlayer_inst/SLICE_52 (from Clock) ROUTE 3 1.676 R7C8B.Q0 to R8C11D.B0 Duration_ms_12 CTOF_DEL --- 0.452 R8C11D.B0 to R8C11D.F0 SLICE_95 ROUTE 2 1.156 R8C11D.F0 to R9C10D.A1 n898 CTOF_DEL --- 0.452 R9C10D.A1 to R9C10D.F1 SLICE_119 ROUTE 2 0.846 R9C10D.F1 to R8C9D.D0 MelodyPlayer_inst/n10 CTOF_DEL --- 0.452 R8C9D.D0 to R8C9D.F0 MelodyPlayer_inst/SLICE_128 ROUTE 6 1.640 R8C9D.F0 to R8C6C.A0 n2177 CTOF_DEL --- 0.452 R8C6C.A0 to R8C6C.F0 SLICE_127 ROUTE 2 0.667 R8C6C.F0 to R8C6A.C0 n2172 CTOF_DEL --- 0.452 R8C6A.C0 to R8C6A.F0 MelodyPlayer_inst/SLICE_148 ROUTE 4 2.186 R8C6A.F0 to R5C10A.CE MelodyPlayer_inst/Clock_enable_65 (to Clock) -------- 10.840 (24.6% logic, 75.4% route), 6 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to MelodyPlayer_inst/SLICE_52: Name Fanout Delay (ns) Site Resource ROUTE 89 3.173 OSC.OSC to R7C8B.CLK Clock -------- 3.173 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to MelodyPlayer_inst/SLICE_158: Name Fanout Delay (ns) Site Resource ROUTE 89 3.173 OSC.OSC to R5C10A.CLK Clock -------- 3.173 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 60.369ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q MelodyPlayer_inst/Duration_ms_i12 (from Clock +) Destination: FF Data in MelodyPlayer_inst/HalfPeriod_us_i9 (to Clock +) FF MelodyPlayer_inst/HalfPeriod_us_i8 Delay: 10.811ns (24.7% logic, 75.3% route), 6 logic levels. Constraint Details: 10.811ns physical path delay MelodyPlayer_inst/SLICE_52 to MelodyPlayer_inst/SLICE_134 meets 71.429ns delay constraint less 0.000ns skew and 0.249ns CE_SET requirement (totaling 71.180ns) by 60.369ns Physical Path Details: Data path MelodyPlayer_inst/SLICE_52 to MelodyPlayer_inst/SLICE_134: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R7C8B.CLK to R7C8B.Q0 MelodyPlayer_inst/SLICE_52 (from Clock) ROUTE 3 1.676 R7C8B.Q0 to R8C11D.B0 Duration_ms_12 CTOF_DEL --- 0.452 R8C11D.B0 to R8C11D.F0 SLICE_95 ROUTE 2 1.156 R8C11D.F0 to R9C10D.A1 n898 CTOF_DEL --- 0.452 R9C10D.A1 to R9C10D.F1 SLICE_119 ROUTE 2 0.846 R9C10D.F1 to R8C9D.D0 MelodyPlayer_inst/n10 CTOF_DEL --- 0.452 R8C9D.D0 to R8C9D.F0 MelodyPlayer_inst/SLICE_128 ROUTE 6 1.640 R8C9D.F0 to R8C6C.A0 n2177 CTOF_DEL --- 0.452 R8C6C.A0 to R8C6C.F0 SLICE_127 ROUTE 2 0.667 R8C6C.F0 to R8C6A.C0 n2172 CTOF_DEL --- 0.452 R8C6A.C0 to R8C6A.F0 MelodyPlayer_inst/SLICE_148 ROUTE 4 2.157 R8C6A.F0 to R5C9D.CE MelodyPlayer_inst/Clock_enable_65 (to Clock) -------- 10.811 (24.7% logic, 75.3% route), 6 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to MelodyPlayer_inst/SLICE_52: Name Fanout Delay (ns) Site Resource ROUTE 89 3.173 OSC.OSC to R7C8B.CLK Clock -------- 3.173 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to MelodyPlayer_inst/SLICE_134: Name Fanout Delay (ns) Site Resource ROUTE 89 3.173 OSC.OSC to R5C9D.CLK Clock -------- 3.173 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 60.681ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q MelodyPlayer_inst/Duration_ms_i13 (from Clock +) Destination: FF Data in MelodyPlayer_inst/HalfPeriod_us_i13 (to Clock +) FF MelodyPlayer_inst/HalfPeriod_us_i12 Delay: 10.499ns (25.4% logic, 74.6% route), 6 logic levels. Constraint Details: 10.499ns physical path delay MelodyPlayer_inst/SLICE_52 to MelodyPlayer_inst/SLICE_158 meets 71.429ns delay constraint less 0.000ns skew and 0.249ns CE_SET requirement (totaling 71.180ns) by 60.681ns Physical Path Details: Data path MelodyPlayer_inst/SLICE_52 to MelodyPlayer_inst/SLICE_158: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R7C8B.CLK to R7C8B.Q1 MelodyPlayer_inst/SLICE_52 (from Clock) ROUTE 3 1.335 R7C8B.Q1 to R8C11D.D0 Duration_ms_13 CTOF_DEL --- 0.452 R8C11D.D0 to R8C11D.F0 SLICE_95 ROUTE 2 1.156 R8C11D.F0 to R9C10D.A1 n898 CTOF_DEL --- 0.452 R9C10D.A1 to R9C10D.F1 SLICE_119 ROUTE 2 0.846 R9C10D.F1 to R8C9D.D0 MelodyPlayer_inst/n10 CTOF_DEL --- 0.452 R8C9D.D0 to R8C9D.F0 MelodyPlayer_inst/SLICE_128 ROUTE 6 1.640 R8C9D.F0 to R8C6C.A0 n2177 CTOF_DEL --- 0.452 R8C6C.A0 to R8C6C.F0 SLICE_127 ROUTE 2 0.667 R8C6C.F0 to R8C6A.C0 n2172 CTOF_DEL --- 0.452 R8C6A.C0 to R8C6A.F0 MelodyPlayer_inst/SLICE_148 ROUTE 4 2.186 R8C6A.F0 to R5C10A.CE MelodyPlayer_inst/Clock_enable_65 (to Clock) -------- 10.499 (25.4% logic, 74.6% route), 6 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to MelodyPlayer_inst/SLICE_52: Name Fanout Delay (ns) Site Resource ROUTE 89 3.173 OSC.OSC to R7C8B.CLK Clock -------- 3.173 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to MelodyPlayer_inst/SLICE_158: Name Fanout Delay (ns) Site Resource ROUTE 89 3.173 OSC.OSC to R5C10A.CLK Clock -------- 3.173 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 60.710ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q MelodyPlayer_inst/Duration_ms_i13 (from Clock +) Destination: FF Data in MelodyPlayer_inst/HalfPeriod_us_i9 (to Clock +) FF MelodyPlayer_inst/HalfPeriod_us_i8 Delay: 10.470ns (25.5% logic, 74.5% route), 6 logic levels. Constraint Details: 10.470ns physical path delay MelodyPlayer_inst/SLICE_52 to MelodyPlayer_inst/SLICE_134 meets 71.429ns delay constraint less 0.000ns skew and 0.249ns CE_SET requirement (totaling 71.180ns) by 60.710ns Physical Path Details: Data path MelodyPlayer_inst/SLICE_52 to MelodyPlayer_inst/SLICE_134: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R7C8B.CLK to R7C8B.Q1 MelodyPlayer_inst/SLICE_52 (from Clock) ROUTE 3 1.335 R7C8B.Q1 to R8C11D.D0 Duration_ms_13 CTOF_DEL --- 0.452 R8C11D.D0 to R8C11D.F0 SLICE_95 ROUTE 2 1.156 R8C11D.F0 to R9C10D.A1 n898 CTOF_DEL --- 0.452 R9C10D.A1 to R9C10D.F1 SLICE_119 ROUTE 2 0.846 R9C10D.F1 to R8C9D.D0 MelodyPlayer_inst/n10 CTOF_DEL --- 0.452 R8C9D.D0 to R8C9D.F0 MelodyPlayer_inst/SLICE_128 ROUTE 6 1.640 R8C9D.F0 to R8C6C.A0 n2177 CTOF_DEL --- 0.452 R8C6C.A0 to R8C6C.F0 SLICE_127 ROUTE 2 0.667 R8C6C.F0 to R8C6A.C0 n2172 CTOF_DEL --- 0.452 R8C6A.C0 to R8C6A.F0 MelodyPlayer_inst/SLICE_148 ROUTE 4 2.157 R8C6A.F0 to R5C9D.CE MelodyPlayer_inst/Clock_enable_65 (to Clock) -------- 10.470 (25.5% logic, 74.5% route), 6 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to MelodyPlayer_inst/SLICE_52: Name Fanout Delay (ns) Site Resource ROUTE 89 3.173 OSC.OSC to R7C8B.CLK Clock -------- 3.173 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to MelodyPlayer_inst/SLICE_134: Name Fanout Delay (ns) Site Resource ROUTE 89 3.173 OSC.OSC to R5C9D.CLK Clock -------- 3.173 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 60.713ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q MelodyPlayer_inst/Duration_ms_i11 (from Clock +) Destination: FF Data in MelodyPlayer_inst/HalfPeriod_us_i13 (to Clock +) FF MelodyPlayer_inst/HalfPeriod_us_i12 Delay: 10.467ns (25.5% logic, 74.5% route), 6 logic levels. Constraint Details: 10.467ns physical path delay MelodyPlayer_inst/SLICE_51 to MelodyPlayer_inst/SLICE_158 meets 71.429ns delay constraint less 0.000ns skew and 0.249ns CE_SET requirement (totaling 71.180ns) by 60.713ns Physical Path Details: Data path MelodyPlayer_inst/SLICE_51 to MelodyPlayer_inst/SLICE_158: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R8C7B.CLK to R8C7B.Q1 MelodyPlayer_inst/SLICE_51 (from Clock) ROUTE 3 2.067 R8C7B.Q1 to R9C10D.A0 Duration_ms_11 CTOF_DEL --- 0.452 R9C10D.A0 to R9C10D.F0 SLICE_119 ROUTE 2 0.392 R9C10D.F0 to R9C10D.C1 Visible_6__N_308 CTOF_DEL --- 0.452 R9C10D.C1 to R9C10D.F1 SLICE_119 ROUTE 2 0.846 R9C10D.F1 to R8C9D.D0 MelodyPlayer_inst/n10 CTOF_DEL --- 0.452 R8C9D.D0 to R8C9D.F0 MelodyPlayer_inst/SLICE_128 ROUTE 6 1.640 R8C9D.F0 to R8C6C.A0 n2177 CTOF_DEL --- 0.452 R8C6C.A0 to R8C6C.F0 SLICE_127 ROUTE 2 0.667 R8C6C.F0 to R8C6A.C0 n2172 CTOF_DEL --- 0.452 R8C6A.C0 to R8C6A.F0 MelodyPlayer_inst/SLICE_148 ROUTE 4 2.186 R8C6A.F0 to R5C10A.CE MelodyPlayer_inst/Clock_enable_65 (to Clock) -------- 10.467 (25.5% logic, 74.5% route), 6 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to MelodyPlayer_inst/SLICE_51: Name Fanout Delay (ns) Site Resource ROUTE 89 3.173 OSC.OSC to R8C7B.CLK Clock -------- 3.173 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to MelodyPlayer_inst/SLICE_158: Name Fanout Delay (ns) Site Resource ROUTE 89 3.173 OSC.OSC to R5C10A.CLK Clock -------- 3.173 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 60.728ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port MelodyPlayer_inst/ROM_inst/mux_71(ASIC) (from Clock +) Destination: FF Data in MelodyPlayer_inst/HalfPeriod_us_i10 (to Clock +) Delay: 10.245ns (55.0% logic, 45.0% route), 3 logic levels. Constraint Details: 10.245ns physical path delay MelodyPlayer_inst/ROM_inst/mux_71 to MelodyPlayer_inst/SLICE_23 meets 71.429ns delay constraint less 0.153ns skew and 0.303ns M_SET requirement (totaling 70.973ns) by 60.728ns Physical Path Details: Data path MelodyPlayer_inst/ROM_inst/mux_71 to MelodyPlayer_inst/SLICE_23: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C1.CLK to EBR_R6C1.DO2 MelodyPlayer_inst/ROM_inst/mux_71 (from Clock) ROUTE 1 2.004 EBR_R6C1.DO2 to R7C7B.B0 MelodyPlayer_inst/ROM_inst/n360 CTOOFX_DEL --- 0.661 R7C7B.B0 to R7C7B.OFX0 MelodyPlayer_inst/ROM_inst/i1569/SLICE_113 ROUTE 2 1.362 R7C7B.OFX0 to R8C7B.B0 MelodyPlayer_inst/ROM_inst/n323 CTOF_DEL --- 0.452 R8C7B.B0 to R8C7B.F0 MelodyPlayer_inst/SLICE_51 ROUTE 2 1.248 R8C7B.F0 to R9C7A.M0 MelodyPlayer_inst/Data_2 (to Clock) -------- 10.245 (55.0% logic, 45.0% route), 3 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to MelodyPlayer_inst/ROM_inst/mux_71: Name Fanout Delay (ns) Site Resource ROUTE 89 3.326 OSC.OSC to EBR_R6C1.CLK Clock -------- 3.326 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to MelodyPlayer_inst/SLICE_23: Name Fanout Delay (ns) Site Resource ROUTE 89 3.173 OSC.OSC to R9C7A.CLK Clock -------- 3.173 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 60.742ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q MelodyPlayer_inst/Duration_ms_i11 (from Clock +) Destination: FF Data in MelodyPlayer_inst/HalfPeriod_us_i9 (to Clock +) FF MelodyPlayer_inst/HalfPeriod_us_i8 Delay: 10.438ns (25.6% logic, 74.4% route), 6 logic levels. Constraint Details: 10.438ns physical path delay MelodyPlayer_inst/SLICE_51 to MelodyPlayer_inst/SLICE_134 meets 71.429ns delay constraint less 0.000ns skew and 0.249ns CE_SET requirement (totaling 71.180ns) by 60.742ns Physical Path Details: Data path MelodyPlayer_inst/SLICE_51 to MelodyPlayer_inst/SLICE_134: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R8C7B.CLK to R8C7B.Q1 MelodyPlayer_inst/SLICE_51 (from Clock) ROUTE 3 2.067 R8C7B.Q1 to R9C10D.A0 Duration_ms_11 CTOF_DEL --- 0.452 R9C10D.A0 to R9C10D.F0 SLICE_119 ROUTE 2 0.392 R9C10D.F0 to R9C10D.C1 Visible_6__N_308 CTOF_DEL --- 0.452 R9C10D.C1 to R9C10D.F1 SLICE_119 ROUTE 2 0.846 R9C10D.F1 to R8C9D.D0 MelodyPlayer_inst/n10 CTOF_DEL --- 0.452 R8C9D.D0 to R8C9D.F0 MelodyPlayer_inst/SLICE_128 ROUTE 6 1.640 R8C9D.F0 to R8C6C.A0 n2177 CTOF_DEL --- 0.452 R8C6C.A0 to R8C6C.F0 SLICE_127 ROUTE 2 0.667 R8C6C.F0 to R8C6A.C0 n2172 CTOF_DEL --- 0.452 R8C6A.C0 to R8C6A.F0 MelodyPlayer_inst/SLICE_148 ROUTE 4 2.157 R8C6A.F0 to R5C9D.CE MelodyPlayer_inst/Clock_enable_65 (to Clock) -------- 10.438 (25.6% logic, 74.4% route), 6 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to MelodyPlayer_inst/SLICE_51: Name Fanout Delay (ns) Site Resource ROUTE 89 3.173 OSC.OSC to R8C7B.CLK Clock -------- 3.173 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to MelodyPlayer_inst/SLICE_134: Name Fanout Delay (ns) Site Resource ROUTE 89 3.173 OSC.OSC to R5C9D.CLK Clock -------- 3.173 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 60.772ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q MelodyPlayer_inst/Duration_ms_i15 (from Clock +) Destination: FF Data in MelodyPlayer_inst/HalfPeriod_us_i13 (to Clock +) FF MelodyPlayer_inst/HalfPeriod_us_i12 Delay: 10.408ns (25.6% logic, 74.4% route), 6 logic levels. Constraint Details: 10.408ns physical path delay MelodyPlayer_inst/SLICE_53 to MelodyPlayer_inst/SLICE_158 meets 71.429ns delay constraint less 0.000ns skew and 0.249ns CE_SET requirement (totaling 71.180ns) by 60.772ns Physical Path Details: Data path MelodyPlayer_inst/SLICE_53 to MelodyPlayer_inst/SLICE_158: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R8C9A.CLK to R8C9A.Q1 MelodyPlayer_inst/SLICE_53 (from Clock) ROUTE 3 1.244 R8C9A.Q1 to R8C11D.A0 Duration_ms_15 CTOF_DEL --- 0.452 R8C11D.A0 to R8C11D.F0 SLICE_95 ROUTE 2 1.156 R8C11D.F0 to R9C10D.A1 n898 CTOF_DEL --- 0.452 R9C10D.A1 to R9C10D.F1 SLICE_119 ROUTE 2 0.846 R9C10D.F1 to R8C9D.D0 MelodyPlayer_inst/n10 CTOF_DEL --- 0.452 R8C9D.D0 to R8C9D.F0 MelodyPlayer_inst/SLICE_128 ROUTE 6 1.640 R8C9D.F0 to R8C6C.A0 n2177 CTOF_DEL --- 0.452 R8C6C.A0 to R8C6C.F0 SLICE_127 ROUTE 2 0.667 R8C6C.F0 to R8C6A.C0 n2172 CTOF_DEL --- 0.452 R8C6A.C0 to R8C6A.F0 MelodyPlayer_inst/SLICE_148 ROUTE 4 2.186 R8C6A.F0 to R5C10A.CE MelodyPlayer_inst/Clock_enable_65 (to Clock) -------- 10.408 (25.6% logic, 74.4% route), 6 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to MelodyPlayer_inst/SLICE_53: Name Fanout Delay (ns) Site Resource ROUTE 89 3.173 OSC.OSC to R8C9A.CLK Clock -------- 3.173 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to MelodyPlayer_inst/SLICE_158: Name Fanout Delay (ns) Site Resource ROUTE 89 3.173 OSC.OSC to R5C10A.CLK Clock -------- 3.173 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 60.801ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q MelodyPlayer_inst/Duration_ms_i15 (from Clock +) Destination: FF Data in MelodyPlayer_inst/HalfPeriod_us_i9 (to Clock +) FF MelodyPlayer_inst/HalfPeriod_us_i8 Delay: 10.379ns (25.7% logic, 74.3% route), 6 logic levels. Constraint Details: 10.379ns physical path delay MelodyPlayer_inst/SLICE_53 to MelodyPlayer_inst/SLICE_134 meets 71.429ns delay constraint less 0.000ns skew and 0.249ns CE_SET requirement (totaling 71.180ns) by 60.801ns Physical Path Details: Data path MelodyPlayer_inst/SLICE_53 to MelodyPlayer_inst/SLICE_134: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R8C9A.CLK to R8C9A.Q1 MelodyPlayer_inst/SLICE_53 (from Clock) ROUTE 3 1.244 R8C9A.Q1 to R8C11D.A0 Duration_ms_15 CTOF_DEL --- 0.452 R8C11D.A0 to R8C11D.F0 SLICE_95 ROUTE 2 1.156 R8C11D.F0 to R9C10D.A1 n898 CTOF_DEL --- 0.452 R9C10D.A1 to R9C10D.F1 SLICE_119 ROUTE 2 0.846 R9C10D.F1 to R8C9D.D0 MelodyPlayer_inst/n10 CTOF_DEL --- 0.452 R8C9D.D0 to R8C9D.F0 MelodyPlayer_inst/SLICE_128 ROUTE 6 1.640 R8C9D.F0 to R8C6C.A0 n2177 CTOF_DEL --- 0.452 R8C6C.A0 to R8C6C.F0 SLICE_127 ROUTE 2 0.667 R8C6C.F0 to R8C6A.C0 n2172 CTOF_DEL --- 0.452 R8C6A.C0 to R8C6A.F0 MelodyPlayer_inst/SLICE_148 ROUTE 4 2.157 R8C6A.F0 to R5C9D.CE MelodyPlayer_inst/Clock_enable_65 (to Clock) -------- 10.379 (25.7% logic, 74.3% route), 6 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to MelodyPlayer_inst/SLICE_53: Name Fanout Delay (ns) Site Resource ROUTE 89 3.173 OSC.OSC to R8C9A.CLK Clock -------- 3.173 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to MelodyPlayer_inst/SLICE_134: Name Fanout Delay (ns) Site Resource ROUTE 89 3.173 OSC.OSC to R5C9D.CLK Clock -------- 3.173 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 60.819ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port MelodyPlayer_inst/ROM_inst/mux_71(ASIC) (from Clock +) Destination: FF Data in MelodyPlayer_inst/HalfPeriod_us_i12 (to Clock +) Delay: 10.154ns (55.5% logic, 44.5% route), 3 logic levels. Constraint Details: 10.154ns physical path delay MelodyPlayer_inst/ROM_inst/mux_71 to MelodyPlayer_inst/SLICE_158 meets 71.429ns delay constraint less 0.153ns skew and 0.303ns M_SET requirement (totaling 70.973ns) by 60.819ns Physical Path Details: Data path MelodyPlayer_inst/ROM_inst/mux_71 to MelodyPlayer_inst/SLICE_158: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C1.CLK to EBR_R6C1.DO4 MelodyPlayer_inst/ROM_inst/mux_71 (from Clock) ROUTE 1 2.037 EBR_R6C1.DO4 to R7C6C.B0 MelodyPlayer_inst/ROM_inst/n358 CTOOFX_DEL --- 0.661 R7C6C.B0 to R7C6C.OFX0 MelodyPlayer_inst/ROM_inst/i1563/SLICE_111 ROUTE 2 1.163 R7C6C.OFX0 to R7C8B.A0 MelodyPlayer_inst/ROM_inst/n321 CTOF_DEL --- 0.452 R7C8B.A0 to R7C8B.F0 MelodyPlayer_inst/SLICE_52 ROUTE 2 1.323 R7C8B.F0 to R5C10A.M0 MelodyPlayer_inst/Data_4 (to Clock) -------- 10.154 (55.5% logic, 44.5% route), 3 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to MelodyPlayer_inst/ROM_inst/mux_71: Name Fanout Delay (ns) Site Resource ROUTE 89 3.326 OSC.OSC to EBR_R6C1.CLK Clock -------- 3.326 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to MelodyPlayer_inst/SLICE_158: Name Fanout Delay (ns) Site Resource ROUTE 89 3.173 OSC.OSC to R5C10A.CLK Clock -------- 3.173 (0.0% logic, 100.0% route), 0 logic levels. Report: 90.179MHz is the maximum frequency for this preference. Report Summary -------------- ---------------------------------------------------------------------------- Preference | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY NET "Clock" 14.000000 MHz ; | 14.000 MHz| 90.179 MHz| 6 | | | ---------------------------------------------------------------------------- All preferences were met. Clock Domains Analysis ------------------------ Found 1 clocks: Clock Domain: Clock Source: OSCH_inst.OSC Loads: 89 Covered under: FREQUENCY NET "Clock" 14.000000 MHz ; Timing summary (Setup): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 6195 paths, 1 nets, and 1185 connections (99.33% coverage) -------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 Sat Sep 23 19:43:24 2023 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Command line: trce -v 10 -gt -sethld -sp 5 -sphld m -o Kurs17_impl1.twr -gui Kurs17_impl1.ncd Kurs17_impl1.prf Design file: kurs17_impl1.ncd Preference file: kurs17_impl1.prf Device,speed: LCMXO2-1200HC,m Report level: verbose report, limited to 10 items per preference -------------------------------------------------------------------------------- Preference Summary
  • FREQUENCY NET "Clock" 14.000000 MHz (0 errors)
  • 4096 items scored, 0 timing errors detected. BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY NET "Clock" 14.000000 MHz ; 4096 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 0.222ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q MelodyPlayer_inst/Address_263__i8 (from Clock +) Destination: SP8KC Port MelodyPlayer_inst/ROM_inst/mux_72(ASIC) (to Clock +) Delay: 0.328ns (40.5% logic, 59.5% route), 1 logic levels. Constraint Details: 0.328ns physical path delay MelodyPlayer_inst/SLICE_9 to MelodyPlayer_inst/ROM_inst/mux_72 meets 0.052ns ADDR_HLD and 0.000ns delay constraint less -0.054ns skew requirement (totaling 0.106ns) by 0.222ns Physical Path Details: Data path MelodyPlayer_inst/SLICE_9 to MelodyPlayer_inst/ROM_inst/mux_72: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R7C5A.CLK to R7C5A.Q1 MelodyPlayer_inst/SLICE_9 (from Clock) ROUTE 5 0.195 R7C5A.Q1 to EBR_R6C4.AD11 MelodyPlayer_inst/Address_8 (to Clock) -------- 0.328 (40.5% logic, 59.5% route), 1 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to MelodyPlayer_inst/SLICE_9: Name Fanout Delay (ns) Site Resource ROUTE 89 1.216 OSC.OSC to R7C5A.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to MelodyPlayer_inst/ROM_inst/mux_72: Name Fanout Delay (ns) Site Resource ROUTE 89 1.270 OSC.OSC to EBR_R6C4.CLK Clock -------- 1.270 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.306ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q EncoderPlay/SynchronizerA/R2_i1 (from Clock +) Destination: FF Data in EncoderPlay/EdgeDetector_inst/Previous_13 (to Clock +) Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. Constraint Details: 0.287ns physical path delay SLICE_95 to SLICE_95 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.306ns Physical Path Details: Data path SLICE_95 to SLICE_95: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R8C11D.CLK to R8C11D.Q1 SLICE_95 (from Clock) ROUTE 4 0.154 R8C11D.Q1 to R8C11D.M0 ButtonState_o (to Clock) -------- 0.287 (46.3% logic, 53.7% route), 1 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_95: Name Fanout Delay (ns) Site Resource ROUTE 89 1.216 OSC.OSC to R8C11D.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_95: Name Fanout Delay (ns) Site Resource ROUTE 89 1.216 OSC.OSC to R8C11D.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.307ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q MelodyPlayer_inst/Address_263__i3 (from Clock +) Destination: SP8KC Port MelodyPlayer_inst/ROM_inst/mux_71(ASIC) (to Clock +) Delay: 0.413ns (32.2% logic, 67.8% route), 1 logic levels. Constraint Details: 0.413ns physical path delay MelodyPlayer_inst/SLICE_13 to MelodyPlayer_inst/ROM_inst/mux_71 meets 0.052ns ADDR_HLD and 0.000ns delay constraint less -0.054ns skew requirement (totaling 0.106ns) by 0.307ns Physical Path Details: Data path MelodyPlayer_inst/SLICE_13 to MelodyPlayer_inst/ROM_inst/mux_71: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R7C4C.CLK to R7C4C.Q0 MelodyPlayer_inst/SLICE_13 (from Clock) ROUTE 5 0.280 R7C4C.Q0 to EBR_R6C1.AD6 MelodyPlayer_inst/Address_3 (to Clock) -------- 0.413 (32.2% logic, 67.8% route), 1 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to MelodyPlayer_inst/SLICE_13: Name Fanout Delay (ns) Site Resource ROUTE 89 1.216 OSC.OSC to R7C4C.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to MelodyPlayer_inst/ROM_inst/mux_71: Name Fanout Delay (ns) Site Resource ROUTE 89 1.270 OSC.OSC to EBR_R6C1.CLK Clock -------- 1.270 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.307ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q MelodyPlayer_inst/Address_263__i5 (from Clock +) Destination: SP8KC Port MelodyPlayer_inst/ROM_inst/mux_72(ASIC) (to Clock +) Delay: 0.413ns (32.2% logic, 67.8% route), 1 logic levels. Constraint Details: 0.413ns physical path delay MelodyPlayer_inst/SLICE_14 to MelodyPlayer_inst/ROM_inst/mux_72 meets 0.052ns ADDR_HLD and 0.000ns delay constraint less -0.054ns skew requirement (totaling 0.106ns) by 0.307ns Physical Path Details: Data path MelodyPlayer_inst/SLICE_14 to MelodyPlayer_inst/ROM_inst/mux_72: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R7C4D.CLK to R7C4D.Q0 MelodyPlayer_inst/SLICE_14 (from Clock) ROUTE 5 0.280 R7C4D.Q0 to EBR_R6C4.AD8 MelodyPlayer_inst/Address_5 (to Clock) -------- 0.413 (32.2% logic, 67.8% route), 1 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to MelodyPlayer_inst/SLICE_14: Name Fanout Delay (ns) Site Resource ROUTE 89 1.216 OSC.OSC to R7C4D.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to MelodyPlayer_inst/ROM_inst/mux_72: Name Fanout Delay (ns) Site Resource ROUTE 89 1.270 OSC.OSC to EBR_R6C4.CLK Clock -------- 1.270 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.343ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q MelodyPlayer_inst/Address_263__i4 (from Clock +) Destination: SP8KC Port MelodyPlayer_inst/ROM_inst/mux_71(ASIC) (to Clock +) Delay: 0.449ns (29.6% logic, 70.4% route), 1 logic levels. Constraint Details: 0.449ns physical path delay MelodyPlayer_inst/SLICE_13 to MelodyPlayer_inst/ROM_inst/mux_71 meets 0.052ns ADDR_HLD and 0.000ns delay constraint less -0.054ns skew requirement (totaling 0.106ns) by 0.343ns Physical Path Details: Data path MelodyPlayer_inst/SLICE_13 to MelodyPlayer_inst/ROM_inst/mux_71: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R7C4C.CLK to R7C4C.Q1 MelodyPlayer_inst/SLICE_13 (from Clock) ROUTE 5 0.316 R7C4C.Q1 to EBR_R6C1.AD7 MelodyPlayer_inst/Address_4 (to Clock) -------- 0.449 (29.6% logic, 70.4% route), 1 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to MelodyPlayer_inst/SLICE_13: Name Fanout Delay (ns) Site Resource ROUTE 89 1.216 OSC.OSC to R7C4C.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to MelodyPlayer_inst/ROM_inst/mux_71: Name Fanout Delay (ns) Site Resource ROUTE 89 1.270 OSC.OSC to EBR_R6C1.CLK Clock -------- 1.270 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.349ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q MelodyPlayer_inst/Address_263__i0 (from Clock +) Destination: SP8KC Port MelodyPlayer_inst/ROM_inst/mux_72(ASIC) (to Clock +) Delay: 0.455ns (29.2% logic, 70.8% route), 1 logic levels. Constraint Details: 0.455ns physical path delay MelodyPlayer_inst/SLICE_8 to MelodyPlayer_inst/ROM_inst/mux_72 meets 0.052ns ADDR_HLD and 0.000ns delay constraint less -0.054ns skew requirement (totaling 0.106ns) by 0.349ns Physical Path Details: Data path MelodyPlayer_inst/SLICE_8 to MelodyPlayer_inst/ROM_inst/mux_72: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R7C4A.CLK to R7C4A.Q1 MelodyPlayer_inst/SLICE_8 (from Clock) ROUTE 5 0.322 R7C4A.Q1 to EBR_R6C4.AD3 MelodyPlayer_inst/Address_0 (to Clock) -------- 0.455 (29.2% logic, 70.8% route), 1 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to MelodyPlayer_inst/SLICE_8: Name Fanout Delay (ns) Site Resource ROUTE 89 1.216 OSC.OSC to R7C4A.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to MelodyPlayer_inst/ROM_inst/mux_72: Name Fanout Delay (ns) Site Resource ROUTE 89 1.270 OSC.OSC to EBR_R6C4.CLK Clock -------- 1.270 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.353ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q MelodyPlayer_inst/Address_263__i9 (from Clock +) Destination: SP8KC Port MelodyPlayer_inst/ROM_inst/mux_72(ASIC) (to Clock +) Delay: 0.459ns (29.0% logic, 71.0% route), 1 logic levels. Constraint Details: 0.459ns physical path delay MelodyPlayer_inst/SLICE_10 to MelodyPlayer_inst/ROM_inst/mux_72 meets 0.052ns ADDR_HLD and 0.000ns delay constraint less -0.054ns skew requirement (totaling 0.106ns) by 0.353ns Physical Path Details: Data path MelodyPlayer_inst/SLICE_10 to MelodyPlayer_inst/ROM_inst/mux_72: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R7C5B.CLK to R7C5B.Q0 MelodyPlayer_inst/SLICE_10 (from Clock) ROUTE 5 0.326 R7C5B.Q0 to EBR_R6C4.AD12 MelodyPlayer_inst/Address_9 (to Clock) -------- 0.459 (29.0% logic, 71.0% route), 1 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to MelodyPlayer_inst/SLICE_10: Name Fanout Delay (ns) Site Resource ROUTE 89 1.216 OSC.OSC to R7C5B.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to MelodyPlayer_inst/ROM_inst/mux_72: Name Fanout Delay (ns) Site Resource ROUTE 89 1.270 OSC.OSC to EBR_R6C4.CLK Clock -------- 1.270 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.353ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q MelodyPlayer_inst/Address_263__i6 (from Clock +) Destination: SP8KC Port MelodyPlayer_inst/ROM_inst/mux_72(ASIC) (to Clock +) Delay: 0.459ns (29.0% logic, 71.0% route), 1 logic levels. Constraint Details: 0.459ns physical path delay MelodyPlayer_inst/SLICE_14 to MelodyPlayer_inst/ROM_inst/mux_72 meets 0.052ns ADDR_HLD and 0.000ns delay constraint less -0.054ns skew requirement (totaling 0.106ns) by 0.353ns Physical Path Details: Data path MelodyPlayer_inst/SLICE_14 to MelodyPlayer_inst/ROM_inst/mux_72: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R7C4D.CLK to R7C4D.Q1 MelodyPlayer_inst/SLICE_14 (from Clock) ROUTE 5 0.326 R7C4D.Q1 to EBR_R6C4.AD9 MelodyPlayer_inst/Address_6 (to Clock) -------- 0.459 (29.0% logic, 71.0% route), 1 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to MelodyPlayer_inst/SLICE_14: Name Fanout Delay (ns) Site Resource ROUTE 89 1.216 OSC.OSC to R7C4D.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to MelodyPlayer_inst/ROM_inst/mux_72: Name Fanout Delay (ns) Site Resource ROUTE 89 1.270 OSC.OSC to EBR_R6C4.CLK Clock -------- 1.270 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DisplayMultiplex_inst/StrobeGenerator0/Counter_i2 (from Clock +) Destination: FF Data in DisplayMultiplex_inst/StrobeGenerator0/Counter_i2 (to Clock +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay DisplayMultiplex_inst/StrobeGenerator0/SLICE_6 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_6 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path DisplayMultiplex_inst/StrobeGenerator0/SLICE_6 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_6: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R8C12B.CLK to R8C12B.Q1 DisplayMultiplex_inst/StrobeGenerator0/SLICE_6 (from Clock) ROUTE 2 0.132 R8C12B.Q1 to R8C12B.A1 DisplayMultiplex_inst/StrobeGenerator0/Counter_2 CTOF_DEL --- 0.101 R8C12B.A1 to R8C12B.F1 DisplayMultiplex_inst/StrobeGenerator0/SLICE_6 ROUTE 1 0.000 R8C12B.F1 to R8C12B.DI1 DisplayMultiplex_inst/StrobeGenerator0/n17 (to Clock) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to DisplayMultiplex_inst/StrobeGenerator0/SLICE_6: Name Fanout Delay (ns) Site Resource ROUTE 89 1.216 OSC.OSC to R8C12B.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to DisplayMultiplex_inst/StrobeGenerator0/SLICE_6: Name Fanout Delay (ns) Site Resource ROUTE 89 1.216 OSC.OSC to R8C12B.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DisplayMultiplex_inst/StrobeGenerator0/Counter_i10 (from Clock +) Destination: FF Data in DisplayMultiplex_inst/StrobeGenerator0/Counter_i10 (to Clock +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay DisplayMultiplex_inst/StrobeGenerator0/SLICE_2 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_2 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path DisplayMultiplex_inst/StrobeGenerator0/SLICE_2 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_2: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R8C13B.CLK to R8C13B.Q1 DisplayMultiplex_inst/StrobeGenerator0/SLICE_2 (from Clock) ROUTE 2 0.132 R8C13B.Q1 to R8C13B.A1 DisplayMultiplex_inst/StrobeGenerator0/Counter_10 CTOF_DEL --- 0.101 R8C13B.A1 to R8C13B.F1 DisplayMultiplex_inst/StrobeGenerator0/SLICE_2 ROUTE 1 0.000 R8C13B.F1 to R8C13B.DI1 DisplayMultiplex_inst/StrobeGenerator0/n9 (to Clock) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to DisplayMultiplex_inst/StrobeGenerator0/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 89 1.216 OSC.OSC to R8C13B.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to DisplayMultiplex_inst/StrobeGenerator0/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 89 1.216 OSC.OSC to R8C13B.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Report Summary -------------- ---------------------------------------------------------------------------- Preference(MIN Delays) | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY NET "Clock" 14.000000 MHz ; | 0.000 ns| 0.222 ns| 1 | | | ---------------------------------------------------------------------------- All preferences were met. Clock Domains Analysis ------------------------ Found 1 clocks: Clock Domain: Clock Source: OSCH_inst.OSC Loads: 89 Covered under: FREQUENCY NET "Clock" 14.000000 MHz ; Timing summary (Hold): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 6195 paths, 1 nets, and 1185 connections (99.33% coverage) Timing summary (Setup and Hold): --------------- Timing errors: 0 (setup), 0 (hold) Score: 0 (setup), 0 (hold) Cumulative negative slack: 0 (0+0) -------------------------------------------------------------------------------- --------------------------------------------------------------------------------