Map TRACE Report

Loading design for application trce from file kurs11_impl1_map.ncd.
Design name: top
NCD version: 3.3
Vendor:      LATTICE
Device:      LCMXO2-1200HC
Package:     TQFP100
Performance: 6
Loading device for application trce from file 'xo2c1200.nph' in environment: D:/Lattice/diamond/3.12/ispfpga.
Package Status:                     Final          Version 1.44.
Performance Hardware Data Status:   Final          Version 34.4.
Setup and Hold Report

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Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
Sat Mar 18 12:11:19 2023

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
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Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o Kurs11_impl1.tw1 -gui -msgset D:/Lattice/Kurs11/promote.xml Kurs11_impl1_map.ncd Kurs11_impl1.prf 
Design file:     kurs11_impl1_map.ncd
Preference file: kurs11_impl1.prf
Device,speed:    LCMXO2-1200HC,6
Report level:    verbose report, limited to 1 item per preference
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Preference Summary

  • FREQUENCY NET "Clock" 133.014099 MHz (194 errors)
  • 616 items scored, 194 timing errors detected. Warning: 103.853MHz is the maximum frequency for this preference. BLOCK ASYNCPATHS BLOCK RESETPATHS BLOCK JTAG PATHS -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY NET "Clock" 133.014099 MHz ; 616 items scored, 194 timing errors detected. -------------------------------------------------------------------------------- Error: The following path exceeds requirements by 2.111ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q A_sync_i1 (from Clock +) Destination: FF Data in Temp_i8 (to Clock +) Delay: 9.496ns (33.9% logic, 66.1% route), 8 logic levels. Constraint Details: 9.496ns physical path delay SLICE_3 to SLICE_16 exceeds 7.518ns delay constraint less 0.133ns DIN_SET requirement (totaling 7.385ns) by 2.111ns Physical Path Details: Data path SLICE_3 to SLICE_16: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.367 SLICE_3.CLK to SLICE_3.Q1 SLICE_3 (from Clock) ROUTE 16 e 0.896 SLICE_3.Q1 to SLICE_32.A0 Y_7_N_1_1 CTOF_DEL --- 0.408 SLICE_32.A0 to SLICE_32.F0 SLICE_32 ROUTE 1 e 0.896 SLICE_32.F0 to SLICE_29.B0 n467 CTOF_DEL --- 0.408 SLICE_29.B0 to SLICE_29.F0 SLICE_29 ROUTE 3 e 0.896 SLICE_29.F0 to SLICE_27.C0 n419 CTOF_DEL --- 0.408 SLICE_27.C0 to SLICE_27.F0 SLICE_27 ROUTE 1 e 0.896 SLICE_27.F0 to SLICE_28.C1 n6 CTOF_DEL --- 0.408 SLICE_28.C1 to SLICE_28.F1 SLICE_28 ROUTE 2 e 0.896 SLICE_28.F1 to SLICE_13.B0 n204 CTOF_DEL --- 0.408 SLICE_13.B0 to SLICE_13.F0 SLICE_13 ROUTE 1 e 0.896 SLICE_13.F0 to SLICE_7.B0 mult_6u_8u_0_pp_2_5 CTOF_DEL --- 0.408 SLICE_7.B0 to SLICE_7.F0 SLICE_7 ROUTE 1 e 0.896 SLICE_7.F0 to SLICE_16.A1 Y_7_N_11_7 CTOF_DEL --- 0.408 SLICE_16.A1 to SLICE_16.F1 SLICE_16 ROUTE 1 e 0.001 SLICE_16.F1 to SLICE_16.DI1 Y_7_N_1_7 (to Clock) -------- 9.496 (33.9% logic, 66.1% route), 8 logic levels. Warning: 103.853MHz is the maximum frequency for this preference. Report Summary -------------- ---------------------------------------------------------------------------- Preference | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY NET "Clock" 133.014099 MHz ; | 133.014 MHz| 103.853 MHz| 8 * | | | ---------------------------------------------------------------------------- 1 preference(marked by "*" above) not met. ---------------------------------------------------------------------------- Critical Nets | Loads| Errors| % of total ---------------------------------------------------------------------------- Y_7_N_1_7 | 1| 176| 90.72% | | | Y_7_N_11_7 | 1| 138| 71.13% | | | s_mult_6u_8u_0_0_4 | 1| 106| 54.64% | | | Y_7_N_1_0 | 15| 97| 50.00% | | | s_mult_6u_8u_0_0_5 | 1| 74| 38.14% | | | n468 | 7| 72| 37.11% | | | Y_7_N_1_1 | 16| 61| 31.44% | | | mco | 1| 56| 28.87% | | | Y_7_N_11_6 | 1| 56| 28.87% | | | co_t_mult_6u_8u_0_1_1 | 1| 50| 25.77% | | | co_mult_6u_8u_0_0_2 | 1| 48| 24.74% | | | n202 | 4| 40| 20.62% | | | mult_6u_8u_0_pp_0_4 | 1| 39| 20.10% | | | n469 | 6| 36| 18.56% | | | mult_6u_8u_0_pp_1_4 | 1| 35| 18.04% | | | mult_6u_8u_0_pp_0_3 | 1| 35| 18.04% | | | n201 | 5| 30| 15.46% | | | co_mult_6u_8u_0_0_1 | 1| 24| 12.37% | | | mult_6u_8u_0_pp_0_2 | 1| 24| 12.37% | | | A_sync_2 | 13| 23| 11.86% | | | mult_6u_8u_0_pp_1_3 | 1| 21| 10.82% | | | ---------------------------------------------------------------------------- Clock Domains Analysis ------------------------ Found 1 clocks: Clock Domain: Clock Source: OSCH_inst.OSC Loads: 12 Covered under: FREQUENCY NET "Clock" 133.014099 MHz ; Timing summary (Setup): --------------- Timing errors: 194 Score: 99840 Cumulative negative slack: 99840 Constraints cover 616 paths, 1 nets, and 167 connections (95.43% coverage) -------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 Sat Mar 18 12:11:20 2023 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o Kurs11_impl1.tw1 -gui -msgset D:/Lattice/Kurs11/promote.xml Kurs11_impl1_map.ncd Kurs11_impl1.prf Design file: kurs11_impl1_map.ncd Preference file: kurs11_impl1.prf Device,speed: LCMXO2-1200HC,M Report level: verbose report, limited to 1 item per preference -------------------------------------------------------------------------------- Preference Summary
  • FREQUENCY NET "Clock" 133.014099 MHz (0 errors)
  • 616 items scored, 0 timing errors detected. BLOCK ASYNCPATHS BLOCK RESETPATHS BLOCK JTAG PATHS -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY NET "Clock" 133.014099 MHz ; 616 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 0.667ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q A_temp_i0 (from Clock +) Destination: FF Data in A_sync_i0 (to Clock +) Delay: 0.648ns (20.5% logic, 79.5% route), 1 logic levels. Constraint Details: 0.648ns physical path delay SLICE_28 to SLICE_3 meets -0.019ns M_HLD and 0.000ns delay constraint requirement (totaling -0.019ns) by 0.667ns Physical Path Details: Data path SLICE_28 to SLICE_3: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 SLICE_28.CLK to SLICE_28.Q1 SLICE_28 (from Clock) ROUTE 1 e 0.515 SLICE_28.Q1 to SLICE_3.M0 A_temp_0 (to Clock) -------- 0.648 (20.5% logic, 79.5% route), 1 logic levels. Report Summary -------------- ---------------------------------------------------------------------------- Preference(MIN Delays) | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY NET "Clock" 133.014099 MHz ; | 0.000 ns| 0.667 ns| 1 | | | ---------------------------------------------------------------------------- All preferences were met. Clock Domains Analysis ------------------------ Found 1 clocks: Clock Domain: Clock Source: OSCH_inst.OSC Loads: 12 Covered under: FREQUENCY NET "Clock" 133.014099 MHz ; Timing summary (Hold): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 616 paths, 1 nets, and 167 connections (95.43% coverage) Timing summary (Setup and Hold): --------------- Timing errors: 194 (setup), 0 (hold) Score: 99840 (setup), 0 (hold) Cumulative negative slack: 99840 (99840+0) -------------------------------------------------------------------------------- --------------------------------------------------------------------------------