Place & Route TRACE Report

Loading design for application trce from file kurs11_impl1.ncd.
Design name: top
NCD version: 3.3
Vendor:      LATTICE
Device:      LCMXO2-1200HC
Package:     TQFP100
Performance: 6
Loading device for application trce from file 'xo2c1200.nph' in environment: D:/Lattice/diamond/3.12/ispfpga.
Package Status:                     Final          Version 1.44.
Performance Hardware Data Status:   Final          Version 34.4.
Setup and Hold Report

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Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
Mon Mar 20 22:03:44 2023

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
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Command line:    trce -v 10 -gt -sethld -sp 6 -sphld m -o Kurs11_impl1.twr -gui -msgset D:/Lattice/Kurs11/promote.xml Kurs11_impl1.ncd Kurs11_impl1.prf 
Design file:     kurs11_impl1.ncd
Preference file: kurs11_impl1.prf
Device,speed:    LCMXO2-1200HC,6
Report level:    verbose report, limited to 10 items per preference
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Preference Summary

  • FREQUENCY NET "Clock" 133.014099 MHz (50 errors)
  • 616 items scored, 50 timing errors detected. Warning: 119.303MHz is the maximum frequency for this preference. BLOCK ASYNCPATHS BLOCK RESETPATHS BLOCK JTAG PATHS -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY NET "Clock" 133.014099 MHz ; 616 items scored, 50 timing errors detected. -------------------------------------------------------------------------------- Error: The following path exceeds requirements by 0.864ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q A_sync_i0 (from Clock +) Destination: FF Data in Temp_i8 (to Clock +) Delay: 8.249ns (50.7% logic, 49.3% route), 8 logic levels. Constraint Details: 8.249ns physical path delay SLICE_3 to SLICE_16 exceeds 7.518ns delay constraint less 0.000ns skew and 0.133ns DIN_SET requirement (totaling 7.385ns) by 0.864ns Physical Path Details: Data path SLICE_3 to SLICE_16: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.367 R8C19A.CLK to R8C19A.Q0 SLICE_3 (from Clock) ROUTE 15 0.839 R8C19A.Q0 to R8C18C.D0 Y_7_N_1_0 CTOF_DEL --- 0.408 R8C18C.D0 to R8C18C.F0 SLICE_28 ROUTE 7 1.163 R8C18C.F0 to R8C17B.B0 n468 CTOF1_DEL --- 0.684 R8C17B.B0 to R8C17B.F1 SLICE_8 ROUTE 1 0.807 R8C17B.F1 to R8C19A.D1 mult_6u_8u_0_pp_0_2 C1TOFCO_DE --- 0.684 R8C19A.D1 to R8C19A.FCO SLICE_3 ROUTE 1 0.000 R8C19A.FCO to R8C19B.FCI co_mult_6u_8u_0_0_1 FCITOF1_DE --- 0.495 R8C19B.FCI to R8C19B.F1 SLICE_4 ROUTE 1 0.501 R8C19B.F1 to R10C19A.D1 s_mult_6u_8u_0_0_4 C1TOFCO_DE --- 0.684 R10C19A.D1 to R10C19A.FCO SLICE_6 ROUTE 1 0.000 R10C19A.FCO to R10C19B.FCI co_t_mult_6u_8u_0_1_1 FCITOF0_DE --- 0.450 R10C19B.FCI to R10C19B.F0 SLICE_7 ROUTE 1 0.759 R10C19B.F0 to R9C19C.A1 Y_7_N_11_7 CTOF_DEL --- 0.408 R9C19C.A1 to R9C19C.F1 SLICE_16 ROUTE 1 0.000 R9C19C.F1 to R9C19C.DI1 Y_7_N_1_7 (to Clock) -------- 8.249 (50.7% logic, 49.3% route), 8 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 12 2.809 OSC.OSC to R8C19A.CLK Clock -------- 2.809 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_16: Name Fanout Delay (ns) Site Resource ROUTE 12 2.809 OSC.OSC to R9C19C.CLK Clock -------- 2.809 (0.0% logic, 100.0% route), 0 logic levels. Error: The following path exceeds requirements by 0.856ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q A_sync_i0 (from Clock +) Destination: FF Data in Temp_i8 (to Clock +) Delay: 8.241ns (51.4% logic, 48.6% route), 8 logic levels. Constraint Details: 8.241ns physical path delay SLICE_3 to SLICE_16 exceeds 7.518ns delay constraint less 0.000ns skew and 0.133ns DIN_SET requirement (totaling 7.385ns) by 0.856ns Physical Path Details: Data path SLICE_3 to SLICE_16: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.367 R8C19A.CLK to R8C19A.Q0 SLICE_3 (from Clock) ROUTE 15 0.839 R8C19A.Q0 to R8C18C.D0 Y_7_N_1_0 CTOF_DEL --- 0.408 R8C18C.D0 to R8C18C.F0 SLICE_28 ROUTE 7 1.163 R8C18C.F0 to R8C17B.B0 n468 C0TOFCO_DE --- 0.787 R8C17B.B0 to R8C17B.FCO SLICE_8 ROUTE 1 0.000 R8C17B.FCO to R8C17C.FCI mco FCITOF0_DE --- 0.450 R8C17C.FCI to R8C17C.F0 SLICE_9 ROUTE 1 0.741 R8C17C.F0 to R8C19B.D0 mult_6u_8u_0_pp_0_3 CTOF1_DEL --- 0.684 R8C19B.D0 to R8C19B.F1 SLICE_4 ROUTE 1 0.501 R8C19B.F1 to R10C19A.D1 s_mult_6u_8u_0_0_4 C1TOFCO_DE --- 0.684 R10C19A.D1 to R10C19A.FCO SLICE_6 ROUTE 1 0.000 R10C19A.FCO to R10C19B.FCI co_t_mult_6u_8u_0_1_1 FCITOF0_DE --- 0.450 R10C19B.FCI to R10C19B.F0 SLICE_7 ROUTE 1 0.759 R10C19B.F0 to R9C19C.A1 Y_7_N_11_7 CTOF_DEL --- 0.408 R9C19C.A1 to R9C19C.F1 SLICE_16 ROUTE 1 0.000 R9C19C.F1 to R9C19C.DI1 Y_7_N_1_7 (to Clock) -------- 8.241 (51.4% logic, 48.6% route), 8 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 12 2.809 OSC.OSC to R8C19A.CLK Clock -------- 2.809 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_16: Name Fanout Delay (ns) Site Resource ROUTE 12 2.809 OSC.OSC to R9C19C.CLK Clock -------- 2.809 (0.0% logic, 100.0% route), 0 logic levels. Error: The following path exceeds requirements by 0.817ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q A_sync_i1 (from Clock +) Destination: FF Data in Temp_i8 (to Clock +) Delay: 8.202ns (39.3% logic, 60.7% route), 8 logic levels. Constraint Details: 8.202ns physical path delay SLICE_3 to SLICE_16 exceeds 7.518ns delay constraint less 0.000ns skew and 0.133ns DIN_SET requirement (totaling 7.385ns) by 0.817ns Physical Path Details: Data path SLICE_3 to SLICE_16: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.367 R8C19A.CLK to R8C19A.Q1 SLICE_3 (from Clock) ROUTE 16 1.127 R8C19A.Q1 to R10C19D.A0 Y_7_N_1_1 CTOF_DEL --- 0.408 R10C19D.A0 to R10C19D.F0 SLICE_32 ROUTE 1 0.242 R10C19D.F0 to R10C19C.D0 n467 CTOF_DEL --- 0.408 R10C19C.D0 to R10C19C.F0 SLICE_29 ROUTE 3 0.494 R10C19C.F0 to R10C18D.D0 n419 CTOF_DEL --- 0.408 R10C18D.D0 to R10C18D.F0 SLICE_27 ROUTE 1 0.501 R10C18D.F0 to R8C18C.D1 n6 CTOF_DEL --- 0.408 R8C18C.D1 to R8C18C.F1 SLICE_28 ROUTE 2 1.051 R8C18C.F1 to R10C18B.B0 n204 CTOF_DEL --- 0.408 R10C18B.B0 to R10C18B.F0 SLICE_13 ROUTE 1 0.805 R10C18B.F0 to R10C19B.B0 mult_6u_8u_0_pp_2_5 CTOF_DEL --- 0.408 R10C19B.B0 to R10C19B.F0 SLICE_7 ROUTE 1 0.759 R10C19B.F0 to R9C19C.A1 Y_7_N_11_7 CTOF_DEL --- 0.408 R9C19C.A1 to R9C19C.F1 SLICE_16 ROUTE 1 0.000 R9C19C.F1 to R9C19C.DI1 Y_7_N_1_7 (to Clock) -------- 8.202 (39.3% logic, 60.7% route), 8 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 12 2.809 OSC.OSC to R8C19A.CLK Clock -------- 2.809 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_16: Name Fanout Delay (ns) Site Resource ROUTE 12 2.809 OSC.OSC to R9C19C.CLK Clock -------- 2.809 (0.0% logic, 100.0% route), 0 logic levels. Error: The following path exceeds requirements by 0.753ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q A_sync_i0 (from Clock +) Destination: FF Data in Temp_i8 (to Clock +) Delay: 8.138ns (50.8% logic, 49.2% route), 8 logic levels. Constraint Details: 8.138ns physical path delay SLICE_3 to SLICE_16 exceeds 7.518ns delay constraint less 0.000ns skew and 0.133ns DIN_SET requirement (totaling 7.385ns) by 0.753ns Physical Path Details: Data path SLICE_3 to SLICE_16: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.367 R8C19A.CLK to R8C19A.Q0 SLICE_3 (from Clock) ROUTE 15 0.839 R8C19A.Q0 to R8C18C.D0 Y_7_N_1_0 CTOF_DEL --- 0.408 R8C18C.D0 to R8C18C.F0 SLICE_28 ROUTE 7 1.163 R8C18C.F0 to R8C17B.B1 n468 C1TOFCO_DE --- 0.684 R8C17B.B1 to R8C17B.FCO SLICE_8 ROUTE 1 0.000 R8C17B.FCO to R8C17C.FCI mco FCITOF0_DE --- 0.450 R8C17C.FCI to R8C17C.F0 SLICE_9 ROUTE 1 0.741 R8C17C.F0 to R8C19B.D0 mult_6u_8u_0_pp_0_3 CTOF1_DEL --- 0.684 R8C19B.D0 to R8C19B.F1 SLICE_4 ROUTE 1 0.501 R8C19B.F1 to R10C19A.D1 s_mult_6u_8u_0_0_4 C1TOFCO_DE --- 0.684 R10C19A.D1 to R10C19A.FCO SLICE_6 ROUTE 1 0.000 R10C19A.FCO to R10C19B.FCI co_t_mult_6u_8u_0_1_1 FCITOF0_DE --- 0.450 R10C19B.FCI to R10C19B.F0 SLICE_7 ROUTE 1 0.759 R10C19B.F0 to R9C19C.A1 Y_7_N_11_7 CTOF_DEL --- 0.408 R9C19C.A1 to R9C19C.F1 SLICE_16 ROUTE 1 0.000 R9C19C.F1 to R9C19C.DI1 Y_7_N_1_7 (to Clock) -------- 8.138 (50.8% logic, 49.2% route), 8 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 12 2.809 OSC.OSC to R8C19A.CLK Clock -------- 2.809 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_16: Name Fanout Delay (ns) Site Resource ROUTE 12 2.809 OSC.OSC to R9C19C.CLK Clock -------- 2.809 (0.0% logic, 100.0% route), 0 logic levels. Error: The following path exceeds requirements by 0.683ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q A_sync_i0 (from Clock +) Destination: FF Data in Temp_i8 (to Clock +) Delay: 8.068ns (50.4% logic, 49.6% route), 8 logic levels. Constraint Details: 8.068ns physical path delay SLICE_3 to SLICE_16 exceeds 7.518ns delay constraint less 0.000ns skew and 0.133ns DIN_SET requirement (totaling 7.385ns) by 0.683ns Physical Path Details: Data path SLICE_3 to SLICE_16: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.367 R8C19A.CLK to R8C19A.Q0 SLICE_3 (from Clock) ROUTE 15 0.839 R8C19A.Q0 to R8C18C.D0 Y_7_N_1_0 CTOF_DEL --- 0.408 R8C18C.D0 to R8C18C.F0 SLICE_28 ROUTE 7 1.163 R8C18C.F0 to R8C17B.B0 n468 C0TOFCO_DE --- 0.787 R8C17B.B0 to R8C17B.FCO SLICE_8 ROUTE 1 0.000 R8C17B.FCO to R8C17C.FCI mco FCITOF0_DE --- 0.450 R8C17C.FCI to R8C17C.F0 SLICE_9 ROUTE 1 0.741 R8C17C.F0 to R8C19B.D0 mult_6u_8u_0_pp_0_3 C0TOFCO_DE --- 0.787 R8C19B.D0 to R8C19B.FCO SLICE_4 ROUTE 1 0.000 R8C19B.FCO to R8C19C.FCI co_mult_6u_8u_0_0_2 FCITOF0_DE --- 0.450 R8C19C.FCI to R8C19C.F0 SLICE_5 ROUTE 1 0.501 R8C19C.F0 to R10C19B.D0 s_mult_6u_8u_0_0_5 CTOF_DEL --- 0.408 R10C19B.D0 to R10C19B.F0 SLICE_7 ROUTE 1 0.759 R10C19B.F0 to R9C19C.A1 Y_7_N_11_7 CTOF_DEL --- 0.408 R9C19C.A1 to R9C19C.F1 SLICE_16 ROUTE 1 0.000 R9C19C.F1 to R9C19C.DI1 Y_7_N_1_7 (to Clock) -------- 8.068 (50.4% logic, 49.6% route), 8 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 12 2.809 OSC.OSC to R8C19A.CLK Clock -------- 2.809 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_16: Name Fanout Delay (ns) Site Resource ROUTE 12 2.809 OSC.OSC to R9C19C.CLK Clock -------- 2.809 (0.0% logic, 100.0% route), 0 logic levels. Error: The following path exceeds requirements by 0.665ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q A_sync_i0 (from Clock +) Destination: FF Data in Temp_i8 (to Clock +) Delay: 8.050ns (49.8% logic, 50.2% route), 8 logic levels. Constraint Details: 8.050ns physical path delay SLICE_3 to SLICE_16 exceeds 7.518ns delay constraint less 0.000ns skew and 0.133ns DIN_SET requirement (totaling 7.385ns) by 0.665ns Physical Path Details: Data path SLICE_3 to SLICE_16: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.367 R8C19A.CLK to R8C19A.Q0 SLICE_3 (from Clock) ROUTE 15 0.839 R8C19A.Q0 to R8C18C.D0 Y_7_N_1_0 CTOF_DEL --- 0.408 R8C18C.D0 to R8C18C.F0 SLICE_28 ROUTE 7 1.163 R8C18C.F0 to R8C17B.B0 n468 C0TOFCO_DE --- 0.787 R8C17B.B0 to R8C17B.FCO SLICE_8 ROUTE 1 0.000 R8C17B.FCO to R8C17C.FCI mco FCITOF1_DE --- 0.495 R8C17C.FCI to R8C17C.F1 SLICE_9 ROUTE 1 0.781 R8C17C.F1 to R8C19B.A1 mult_6u_8u_0_pp_0_4 C1TOFCO_DE --- 0.684 R8C19B.A1 to R8C19B.FCO SLICE_4 ROUTE 1 0.000 R8C19B.FCO to R8C19C.FCI co_mult_6u_8u_0_0_2 FCITOF0_DE --- 0.450 R8C19C.FCI to R8C19C.F0 SLICE_5 ROUTE 1 0.501 R8C19C.F0 to R10C19B.D0 s_mult_6u_8u_0_0_5 CTOF_DEL --- 0.408 R10C19B.D0 to R10C19B.F0 SLICE_7 ROUTE 1 0.759 R10C19B.F0 to R9C19C.A1 Y_7_N_11_7 CTOF_DEL --- 0.408 R9C19C.A1 to R9C19C.F1 SLICE_16 ROUTE 1 0.000 R9C19C.F1 to R9C19C.DI1 Y_7_N_1_7 (to Clock) -------- 8.050 (49.8% logic, 50.2% route), 8 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 12 2.809 OSC.OSC to R8C19A.CLK Clock -------- 2.809 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_16: Name Fanout Delay (ns) Site Resource ROUTE 12 2.809 OSC.OSC to R9C19C.CLK Clock -------- 2.809 (0.0% logic, 100.0% route), 0 logic levels. Error: The following path exceeds requirements by 0.665ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q A_sync_i0 (from Clock +) Destination: FF Data in Temp_i8 (to Clock +) Delay: 8.050ns (49.8% logic, 50.2% route), 8 logic levels. Constraint Details: 8.050ns physical path delay SLICE_3 to SLICE_16 exceeds 7.518ns delay constraint less 0.000ns skew and 0.133ns DIN_SET requirement (totaling 7.385ns) by 0.665ns Physical Path Details: Data path SLICE_3 to SLICE_16: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.367 R8C19A.CLK to R8C19A.Q0 SLICE_3 (from Clock) ROUTE 15 0.839 R8C19A.Q0 to R8C18C.D0 Y_7_N_1_0 CTOF_DEL --- 0.408 R8C18C.D0 to R8C18C.F0 SLICE_28 ROUTE 7 1.163 R8C18C.F0 to R8C17B.B0 n468 C0TOFCO_DE --- 0.787 R8C17B.B0 to R8C17B.FCO SLICE_8 ROUTE 1 0.000 R8C17B.FCO to R8C17C.FCI mco FCITOF1_DE --- 0.495 R8C17C.FCI to R8C17C.F1 SLICE_9 ROUTE 1 0.781 R8C17C.F1 to R8C19B.A1 mult_6u_8u_0_pp_0_4 CTOF_DEL --- 0.408 R8C19B.A1 to R8C19B.F1 SLICE_4 ROUTE 1 0.501 R8C19B.F1 to R10C19A.D1 s_mult_6u_8u_0_0_4 C1TOFCO_DE --- 0.684 R10C19A.D1 to R10C19A.FCO SLICE_6 ROUTE 1 0.000 R10C19A.FCO to R10C19B.FCI co_t_mult_6u_8u_0_1_1 FCITOF0_DE --- 0.450 R10C19B.FCI to R10C19B.F0 SLICE_7 ROUTE 1 0.759 R10C19B.F0 to R9C19C.A1 Y_7_N_11_7 CTOF_DEL --- 0.408 R9C19C.A1 to R9C19C.F1 SLICE_16 ROUTE 1 0.000 R9C19C.F1 to R9C19C.DI1 Y_7_N_1_7 (to Clock) -------- 8.050 (49.8% logic, 50.2% route), 8 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 12 2.809 OSC.OSC to R8C19A.CLK Clock -------- 2.809 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_16: Name Fanout Delay (ns) Site Resource ROUTE 12 2.809 OSC.OSC to R9C19C.CLK Clock -------- 2.809 (0.0% logic, 100.0% route), 0 logic levels. Error: The following path exceeds requirements by 0.661ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q A_sync_i1 (from Clock +) Destination: FF Data in Temp_i8 (to Clock +) Delay: 8.046ns (52.0% logic, 48.0% route), 8 logic levels. Constraint Details: 8.046ns physical path delay SLICE_3 to SLICE_16 exceeds 7.518ns delay constraint less 0.000ns skew and 0.133ns DIN_SET requirement (totaling 7.385ns) by 0.661ns Physical Path Details: Data path SLICE_3 to SLICE_16: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.367 R8C19A.CLK to R8C19A.Q1 SLICE_3 (from Clock) ROUTE 16 0.636 R8C19A.Q1 to R8C18C.C0 Y_7_N_1_1 CTOF_DEL --- 0.408 R8C18C.C0 to R8C18C.F0 SLICE_28 ROUTE 7 1.163 R8C18C.F0 to R8C17B.B0 n468 CTOF1_DEL --- 0.684 R8C17B.B0 to R8C17B.F1 SLICE_8 ROUTE 1 0.807 R8C17B.F1 to R8C19A.D1 mult_6u_8u_0_pp_0_2 C1TOFCO_DE --- 0.684 R8C19A.D1 to R8C19A.FCO SLICE_3 ROUTE 1 0.000 R8C19A.FCO to R8C19B.FCI co_mult_6u_8u_0_0_1 FCITOF1_DE --- 0.495 R8C19B.FCI to R8C19B.F1 SLICE_4 ROUTE 1 0.501 R8C19B.F1 to R10C19A.D1 s_mult_6u_8u_0_0_4 C1TOFCO_DE --- 0.684 R10C19A.D1 to R10C19A.FCO SLICE_6 ROUTE 1 0.000 R10C19A.FCO to R10C19B.FCI co_t_mult_6u_8u_0_1_1 FCITOF0_DE --- 0.450 R10C19B.FCI to R10C19B.F0 SLICE_7 ROUTE 1 0.759 R10C19B.F0 to R9C19C.A1 Y_7_N_11_7 CTOF_DEL --- 0.408 R9C19C.A1 to R9C19C.F1 SLICE_16 ROUTE 1 0.000 R9C19C.F1 to R9C19C.DI1 Y_7_N_1_7 (to Clock) -------- 8.046 (52.0% logic, 48.0% route), 8 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 12 2.809 OSC.OSC to R8C19A.CLK Clock -------- 2.809 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_16: Name Fanout Delay (ns) Site Resource ROUTE 12 2.809 OSC.OSC to R9C19C.CLK Clock -------- 2.809 (0.0% logic, 100.0% route), 0 logic levels. Error: The following path exceeds requirements by 0.653ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q A_sync_i1 (from Clock +) Destination: FF Data in Temp_i8 (to Clock +) Delay: 8.038ns (52.7% logic, 47.3% route), 8 logic levels. Constraint Details: 8.038ns physical path delay SLICE_3 to SLICE_16 exceeds 7.518ns delay constraint less 0.000ns skew and 0.133ns DIN_SET requirement (totaling 7.385ns) by 0.653ns Physical Path Details: Data path SLICE_3 to SLICE_16: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.367 R8C19A.CLK to R8C19A.Q1 SLICE_3 (from Clock) ROUTE 16 0.636 R8C19A.Q1 to R8C18C.C0 Y_7_N_1_1 CTOF_DEL --- 0.408 R8C18C.C0 to R8C18C.F0 SLICE_28 ROUTE 7 1.163 R8C18C.F0 to R8C17B.B0 n468 C0TOFCO_DE --- 0.787 R8C17B.B0 to R8C17B.FCO SLICE_8 ROUTE 1 0.000 R8C17B.FCO to R8C17C.FCI mco FCITOF0_DE --- 0.450 R8C17C.FCI to R8C17C.F0 SLICE_9 ROUTE 1 0.741 R8C17C.F0 to R8C19B.D0 mult_6u_8u_0_pp_0_3 CTOF1_DEL --- 0.684 R8C19B.D0 to R8C19B.F1 SLICE_4 ROUTE 1 0.501 R8C19B.F1 to R10C19A.D1 s_mult_6u_8u_0_0_4 C1TOFCO_DE --- 0.684 R10C19A.D1 to R10C19A.FCO SLICE_6 ROUTE 1 0.000 R10C19A.FCO to R10C19B.FCI co_t_mult_6u_8u_0_1_1 FCITOF0_DE --- 0.450 R10C19B.FCI to R10C19B.F0 SLICE_7 ROUTE 1 0.759 R10C19B.F0 to R9C19C.A1 Y_7_N_11_7 CTOF_DEL --- 0.408 R9C19C.A1 to R9C19C.F1 SLICE_16 ROUTE 1 0.000 R9C19C.F1 to R9C19C.DI1 Y_7_N_1_7 (to Clock) -------- 8.038 (52.7% logic, 47.3% route), 8 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 12 2.809 OSC.OSC to R8C19A.CLK Clock -------- 2.809 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_16: Name Fanout Delay (ns) Site Resource ROUTE 12 2.809 OSC.OSC to R9C19C.CLK Clock -------- 2.809 (0.0% logic, 100.0% route), 0 logic levels. Error: The following path exceeds requirements by 0.588ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q A_sync_i0 (from Clock +) Destination: FF Data in Temp_i8 (to Clock +) Delay: 7.973ns (49.0% logic, 51.0% route), 8 logic levels. Constraint Details: 7.973ns physical path delay SLICE_3 to SLICE_16 exceeds 7.518ns delay constraint less 0.000ns skew and 0.133ns DIN_SET requirement (totaling 7.385ns) by 0.588ns Physical Path Details: Data path SLICE_3 to SLICE_16: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.367 R8C19A.CLK to R8C19A.Q0 SLICE_3 (from Clock) ROUTE 15 0.839 R8C19A.Q0 to R8C18C.D0 Y_7_N_1_0 CTOF_DEL --- 0.408 R8C18C.D0 to R8C18C.F0 SLICE_28 ROUTE 7 1.163 R8C18C.F0 to R8C17B.B1 n468 CTOF_DEL --- 0.408 R8C17B.B1 to R8C17B.F1 SLICE_8 ROUTE 1 0.807 R8C17B.F1 to R8C19A.D1 mult_6u_8u_0_pp_0_2 C1TOFCO_DE --- 0.684 R8C19A.D1 to R8C19A.FCO SLICE_3 ROUTE 1 0.000 R8C19A.FCO to R8C19B.FCI co_mult_6u_8u_0_0_1 FCITOF1_DE --- 0.495 R8C19B.FCI to R8C19B.F1 SLICE_4 ROUTE 1 0.501 R8C19B.F1 to R10C19A.D1 s_mult_6u_8u_0_0_4 C1TOFCO_DE --- 0.684 R10C19A.D1 to R10C19A.FCO SLICE_6 ROUTE 1 0.000 R10C19A.FCO to R10C19B.FCI co_t_mult_6u_8u_0_1_1 FCITOF0_DE --- 0.450 R10C19B.FCI to R10C19B.F0 SLICE_7 ROUTE 1 0.759 R10C19B.F0 to R9C19C.A1 Y_7_N_11_7 CTOF_DEL --- 0.408 R9C19C.A1 to R9C19C.F1 SLICE_16 ROUTE 1 0.000 R9C19C.F1 to R9C19C.DI1 Y_7_N_1_7 (to Clock) -------- 7.973 (49.0% logic, 51.0% route), 8 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 12 2.809 OSC.OSC to R8C19A.CLK Clock -------- 2.809 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_16: Name Fanout Delay (ns) Site Resource ROUTE 12 2.809 OSC.OSC to R9C19C.CLK Clock -------- 2.809 (0.0% logic, 100.0% route), 0 logic levels. Warning: 119.303MHz is the maximum frequency for this preference. Report Summary -------------- ---------------------------------------------------------------------------- Preference | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY NET "Clock" 133.014099 MHz ; | 133.014 MHz| 119.303 MHz| 8 * | | | ---------------------------------------------------------------------------- 1 preference(marked by "*" above) not met. ---------------------------------------------------------------------------- Critical Nets | Loads| Errors| % of total ---------------------------------------------------------------------------- Y_7_N_1_7 | 1| 47| 94.00% | | | Y_7_N_11_7 | 1| 37| 74.00% | | | n468 | 7| 35| 70.00% | | | s_mult_6u_8u_0_0_4 | 1| 27| 54.00% | | | mco | 1| 25| 50.00% | | | Y_7_N_1_0 | 15| 22| 44.00% | | | Y_7_N_1_1 | 16| 18| 36.00% | | | co_t_mult_6u_8u_0_1_1 | 1| 14| 28.00% | | | s_mult_6u_8u_0_0_5 | 1| 14| 28.00% | | | mult_6u_8u_0_pp_0_3 | 1| 14| 28.00% | | | Y_7_N_11_6 | 1| 13| 26.00% | | | co_mult_6u_8u_0_0_2 | 1| 12| 24.00% | | | mult_6u_8u_0_pp_0_4 | 1| 11| 22.00% | | | co_mult_6u_8u_0_0_1 | 1| 10| 20.00% | | | mult_6u_8u_0_pp_0_2 | 1| 10| 20.00% | | | n204 | 2| 9| 18.00% | | | mult_6u_8u_0_pp_2_5 | 1| 9| 18.00% | | | n6 | 1| 7| 14.00% | | | n202 | 4| 6| 12.00% | | | ---------------------------------------------------------------------------- Clock Domains Analysis ------------------------ Found 1 clocks: Clock Domain: Clock Source: OSCH_inst.OSC Loads: 12 Covered under: FREQUENCY NET "Clock" 133.014099 MHz ; Timing summary (Setup): --------------- Timing errors: 50 Score: 19106 Cumulative negative slack: 19106 Constraints cover 616 paths, 1 nets, and 167 connections (95.43% coverage) -------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 Mon Mar 20 22:03:44 2023 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Command line: trce -v 10 -gt -sethld -sp 6 -sphld m -o Kurs11_impl1.twr -gui -msgset D:/Lattice/Kurs11/promote.xml Kurs11_impl1.ncd Kurs11_impl1.prf Design file: kurs11_impl1.ncd Preference file: kurs11_impl1.prf Device,speed: LCMXO2-1200HC,m Report level: verbose report, limited to 10 items per preference -------------------------------------------------------------------------------- Preference Summary
  • FREQUENCY NET "Clock" 133.014099 MHz (0 errors)
  • 616 items scored, 0 timing errors detected. BLOCK ASYNCPATHS BLOCK RESETPATHS BLOCK JTAG PATHS -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY NET "Clock" 133.014099 MHz ; 616 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 0.304ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q A_temp_i3 (from Clock +) Destination: FF Data in A_sync_i3 (to Clock +) Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. Constraint Details: 0.285ns physical path delay SLICE_29 to SLICE_6 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.304ns Physical Path Details: Data path SLICE_29 to SLICE_6: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R10C19C.CLK to R10C19C.Q0 SLICE_29 (from Clock) ROUTE 1 0.152 R10C19C.Q0 to R10C19A.M1 A_temp_3 (to Clock) -------- 0.285 (46.7% logic, 53.3% route), 1 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_29: Name Fanout Delay (ns) Site Resource ROUTE 12 1.216 OSC.OSC to R10C19C.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_6: Name Fanout Delay (ns) Site Resource ROUTE 12 1.216 OSC.OSC to R10C19A.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.304ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q A_temp_i7 (from Clock +) Destination: FF Data in A_sync_i7 (to Clock +) Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. Constraint Details: 0.285ns physical path delay SLICE_30 to SLICE_28 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.304ns Physical Path Details: Data path SLICE_30 to SLICE_28: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R8C18A.CLK to R8C18A.Q0 SLICE_30 (from Clock) ROUTE 1 0.152 R8C18A.Q0 to R8C18C.M0 A_temp_7 (to Clock) -------- 0.285 (46.7% logic, 53.3% route), 1 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_30: Name Fanout Delay (ns) Site Resource ROUTE 12 1.216 OSC.OSC to R8C18A.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_28: Name Fanout Delay (ns) Site Resource ROUTE 12 1.216 OSC.OSC to R8C18C.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.304ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q A_temp_i2 (from Clock +) Destination: FF Data in A_sync_i2 (to Clock +) Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. Constraint Details: 0.285ns physical path delay SLICE_32 to SLICE_6 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.304ns Physical Path Details: Data path SLICE_32 to SLICE_6: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R10C19D.CLK to R10C19D.Q1 SLICE_32 (from Clock) ROUTE 1 0.152 R10C19D.Q1 to R10C19A.M0 A_temp_2 (to Clock) -------- 0.285 (46.7% logic, 53.3% route), 1 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_32: Name Fanout Delay (ns) Site Resource ROUTE 12 1.216 OSC.OSC to R10C19D.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_6: Name Fanout Delay (ns) Site Resource ROUTE 12 1.216 OSC.OSC to R10C19A.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.306ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q A_temp_i5 (from Clock +) Destination: FF Data in A_sync_i5 (to Clock +) Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. Constraint Details: 0.287ns physical path delay SLICE_31 to SLICE_33 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.306ns Physical Path Details: Data path SLICE_31 to SLICE_33: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R8C20D.CLK to R8C20D.Q0 SLICE_31 (from Clock) ROUTE 1 0.154 R8C20D.Q0 to R8C19D.M0 A_temp_5 (to Clock) -------- 0.287 (46.3% logic, 53.7% route), 1 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_31: Name Fanout Delay (ns) Site Resource ROUTE 12 1.216 OSC.OSC to R8C20D.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_33: Name Fanout Delay (ns) Site Resource ROUTE 12 1.216 OSC.OSC to R8C19D.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.318ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q A_sync_i0 (from Clock +) Destination: FF Data in Temp_i1 (to Clock +) Delay: 0.299ns (44.5% logic, 55.5% route), 1 logic levels. Constraint Details: 0.299ns physical path delay SLICE_3 to SLICE_30 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.318ns Physical Path Details: Data path SLICE_3 to SLICE_30: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R8C19A.CLK to R8C19A.Q0 SLICE_3 (from Clock) ROUTE 15 0.166 R8C19A.Q0 to R8C18A.M1 Y_7_N_1_0 (to Clock) -------- 0.299 (44.5% logic, 55.5% route), 1 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 12 1.216 OSC.OSC to R8C19A.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_30: Name Fanout Delay (ns) Site Resource ROUTE 12 1.216 OSC.OSC to R8C18A.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.418ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q A_temp_i0 (from Clock +) Destination: FF Data in A_sync_i0 (to Clock +) Delay: 0.399ns (33.3% logic, 66.7% route), 1 logic levels. Constraint Details: 0.399ns physical path delay SLICE_28 to SLICE_3 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.418ns Physical Path Details: Data path SLICE_28 to SLICE_3: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R8C18C.CLK to R8C18C.Q1 SLICE_28 (from Clock) ROUTE 1 0.266 R8C18C.Q1 to R8C19A.M0 A_temp_0 (to Clock) -------- 0.399 (33.3% logic, 66.7% route), 1 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_28: Name Fanout Delay (ns) Site Resource ROUTE 12 1.216 OSC.OSC to R8C18C.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 12 1.216 OSC.OSC to R8C19A.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.418ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q A_temp_i4 (from Clock +) Destination: FF Data in A_sync_i4 (to Clock +) Delay: 0.399ns (33.3% logic, 66.7% route), 1 logic levels. Constraint Details: 0.399ns physical path delay SLICE_29 to SLICE_15 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.418ns Physical Path Details: Data path SLICE_29 to SLICE_15: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R10C19C.CLK to R10C19C.Q1 SLICE_29 (from Clock) ROUTE 1 0.266 R10C19C.Q1 to R9C19A.M0 A_temp_4 (to Clock) -------- 0.399 (33.3% logic, 66.7% route), 1 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_29: Name Fanout Delay (ns) Site Resource ROUTE 12 1.216 OSC.OSC to R10C19C.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_15: Name Fanout Delay (ns) Site Resource ROUTE 12 1.216 OSC.OSC to R9C19A.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.418ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q A_temp_i1 (from Clock +) Destination: FF Data in A_sync_i1 (to Clock +) Delay: 0.399ns (33.3% logic, 66.7% route), 1 logic levels. Constraint Details: 0.399ns physical path delay SLICE_32 to SLICE_3 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.418ns Physical Path Details: Data path SLICE_32 to SLICE_3: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R10C19D.CLK to R10C19D.Q0 SLICE_32 (from Clock) ROUTE 1 0.266 R10C19D.Q0 to R8C19A.M1 A_temp_1 (to Clock) -------- 0.399 (33.3% logic, 66.7% route), 1 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_32: Name Fanout Delay (ns) Site Resource ROUTE 12 1.216 OSC.OSC to R10C19D.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 12 1.216 OSC.OSC to R8C19A.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.461ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q A_sync_i5 (from Clock +) Destination: FF Data in Temp_i6 (to Clock +) Delay: 0.448ns (52.2% logic, 47.8% route), 2 logic levels. Constraint Details: 0.448ns physical path delay SLICE_33 to SLICE_14 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.461ns Physical Path Details: Data path SLICE_33 to SLICE_14: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R8C19D.CLK to R8C19D.Q0 SLICE_33 (from Clock) ROUTE 4 0.214 R8C19D.Q0 to R9C19B.A1 A_sync_5 CTOF_DEL --- 0.101 R9C19B.A1 to R9C19B.F1 SLICE_14 ROUTE 1 0.000 R9C19B.F1 to R9C19B.DI1 Y_7_N_1_5 (to Clock) -------- 0.448 (52.2% logic, 47.8% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_33: Name Fanout Delay (ns) Site Resource ROUTE 12 1.216 OSC.OSC to R8C19D.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_14: Name Fanout Delay (ns) Site Resource ROUTE 12 1.216 OSC.OSC to R9C19B.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.472ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q A_sync_i4 (from Clock +) Destination: FF Data in Temp_i5 (to Clock +) Delay: 0.459ns (51.0% logic, 49.0% route), 2 logic levels. Constraint Details: 0.459ns physical path delay SLICE_15 to SLICE_14 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.472ns Physical Path Details: Data path SLICE_15 to SLICE_14: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R9C19A.CLK to R9C19A.Q0 SLICE_15 (from Clock) ROUTE 6 0.225 R9C19A.Q0 to R9C19B.B0 A_sync_4 CTOF_DEL --- 0.101 R9C19B.B0 to R9C19B.F0 SLICE_14 ROUTE 1 0.000 R9C19B.F0 to R9C19B.DI0 Y_7_N_1_4 (to Clock) -------- 0.459 (51.0% logic, 49.0% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_15: Name Fanout Delay (ns) Site Resource ROUTE 12 1.216 OSC.OSC to R9C19A.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_14: Name Fanout Delay (ns) Site Resource ROUTE 12 1.216 OSC.OSC to R9C19B.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Report Summary -------------- ---------------------------------------------------------------------------- Preference(MIN Delays) | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY NET "Clock" 133.014099 MHz ; | 0.000 ns| 0.304 ns| 1 | | | ---------------------------------------------------------------------------- All preferences were met. Clock Domains Analysis ------------------------ Found 1 clocks: Clock Domain: Clock Source: OSCH_inst.OSC Loads: 12 Covered under: FREQUENCY NET "Clock" 133.014099 MHz ; Timing summary (Hold): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 616 paths, 1 nets, and 167 connections (95.43% coverage) Timing summary (Setup and Hold): --------------- Timing errors: 50 (setup), 0 (hold) Score: 19106 (setup), 0 (hold) Cumulative negative slack: 19106 (19106+0) -------------------------------------------------------------------------------- --------------------------------------------------------------------------------