Synthesis and Ngdbuild Report synthesis: version Diamond (64-bit) 3.12.1.454 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Thu Mar 23 22:06:33 2023 Command Line: synthesis -f Kurs11_impl1_lattice.synproj -gui -msgset D:/Lattice/Kurs11/promote.xml Synthesis options: The -a option is MachXO2. The -s option is 6. The -t option is TQFP100. The -d option is LCMXO2-1200HC. Using package TQFP100. Using performance grade 6. ########################################################## ### Lattice Family : MachXO2 ### Device : LCMXO2-1200HC ### Package : TQFP100 ### Speed : 6 ########################################################## INFO - synthesis: User-Selected Strategy Settings Optimization goal = Balanced Top-level module name = top. Target frequency = 200.000000 MHz. Maximum fanout = 1000. Timing path count = 3 BRAM utilization = 100.000000 % DSP usage = true DSP utilization = 100.000000 % fsm_encoding_style = auto resolve_mixed_drivers = 0 fix_gated_clocks = 1 Mux style = Auto Use Carry Chain = true carry_chain_length = 0 Loop Limit = 1950. Use IO Insertion = TRUE Use IO Reg = AUTO Resource Sharing = TRUE Propagate Constants = TRUE Remove Duplicate Registers = TRUE force_gsr = auto ROM style = auto RAM style = auto The -comp option is FALSE. The -syn option is FALSE. -p D:/Lattice/Kurs11 (searchpath added) -p D:/Lattice/diamond/3.12/ispfpga/xo2c00/data (searchpath added) -p D:/Lattice/Kurs11/impl1 (searchpath added) -p D:/Lattice/Kurs11 (searchpath added) Verilog design file = D:/Lattice/Kurs11/impl1/source/top.v NGD file = Kurs11_impl1.ngd -sdc option: SDC file input is D:/Lattice/Kurs11/impl1/source/timing.ldc. -lpf option: Output file option is ON. Hardtimer checking is enabled (default). The -dt option is not used. The -r option is OFF. [ Remove LOC Properties is OFF. ] Technology check ok... Analyzing Verilog file D:/Lattice/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482 Compile design. Compile Design Begin Analyzing Verilog file d:/lattice/kurs11/impl1/source/top.v. VERI-1482 Analyzing Verilog file D:/Lattice/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482 Top module name (Verilog): top INFO - synthesis: d:/lattice/kurs11/impl1/source/top.v(1): compiling module top. VERI-1018 INFO - synthesis: D:/Lattice/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1793): compiling module OSCH(NOM_FREQ="133.00"). VERI-1018 Loading NGL library 'D:/Lattice/diamond/3.12/ispfpga/xo2c00a/data/xo2alib.ngl'... Loading NGL library 'D:/Lattice/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'... Loading NGL library 'D:/Lattice/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... Loading NGL library 'D:/Lattice/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... Loading device for application map from file 'xo2c1200.nph' in environment: D:/Lattice/diamond/3.12/ispfpga. Package Status: Final Version 1.44. Top-level module name = top. Analyzing Verilog file D:/Lattice/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482 Analyzing Verilog file mult_6u_8u.v. VERI-1482 WARNING - synthesis: net \/a1[11] does not have a driver. VDB-1002 WARNING - synthesis: net \/a0[0] does not have a driver. VDB-1002 WARNING - synthesis: net \/a0[1] does not have a driver. VDB-1002 WARNING - synthesis: net \/a0[2] does not have a driver. VDB-1002 WARNING - synthesis: net \/a0[3] does not have a driver. VDB-1002 WARNING - synthesis: net \/a0[4] does not have a driver. VDB-1002 WARNING - synthesis: net \/a0[5] does not have a driver. VDB-1002 WARNING - synthesis: net \/a0[6] does not have a driver. VDB-1002 WARNING - synthesis: net \/a0[11] does not have a driver. VDB-1002 WARNING - synthesis: net \/a0[10] does not have a driver. VDB-1002 WARNING - synthesis: net \/a0[9] does not have a driver. VDB-1002 WARNING - synthesis: net \/a0[8] does not have a driver. VDB-1002 WARNING - synthesis: net \/a0[7] does not have a driver. VDB-1002 WARNING - synthesis: net \/a2[8] does not have a driver. VDB-1002 WARNING - synthesis: net \/a2[9] does not have a driver. VDB-1002 WARNING - synthesis: net \/a2[10] does not have a driver. VDB-1002 WARNING - synthesis: net \/a2[11] does not have a driver. VDB-1002 WARNING - synthesis: net \/a1[0] does not have a driver. VDB-1002 WARNING - synthesis: net \/a1[1] does not have a driver. VDB-1002 WARNING - synthesis: net \/a1[2] does not have a driver. VDB-1002 WARNING - synthesis: net \/a1[3] does not have a driver. VDB-1002 WARNING - synthesis: net \/a1[4] does not have a driver. VDB-1002 WARNING - synthesis: net \/a1[5] does not have a driver. VDB-1002 WARNING - synthesis: net \/a1[6] does not have a driver. VDB-1002 WARNING - synthesis: net \/a1[7] does not have a driver. VDB-1002 WARNING - synthesis: net \/a1[8] does not have a driver. VDB-1002 WARNING - synthesis: net \/a1[9] does not have a driver. VDB-1002 WARNING - synthesis: net \/a1[10] does not have a driver. VDB-1002 WARNING - synthesis: net \/a2[7] does not have a driver. VDB-1002 WARNING - synthesis: net \/a2[6] does not have a driver. VDB-1002 WARNING - synthesis: net \/a2[5] does not have a driver. VDB-1002 WARNING - synthesis: net \/a2[4] does not have a driver. VDB-1002 WARNING - synthesis: net \/a2[3] does not have a driver. VDB-1002 WARNING - synthesis: net \/a2[2] does not have a driver. VDB-1002 WARNING - synthesis: net \/a2[1] does not have a driver. VDB-1002 WARNING - synthesis: net \/a2[0] does not have a driver. VDB-1002 WARNING - synthesis: d:/lattice/kurs11/impl1/source/top.v(38): input port a[5] is not connected on this instance. VDB-1013 GSR instance connected to net Reset_c. Writing LPF file Kurs11_impl1.lpf. Results of NGD DRC are available in top_drc.log. Loading NGL library 'D:/Lattice/diamond/3.12/ispfpga/xo2c00a/data/xo2alib.ngl'... Loading NGL library 'D:/Lattice/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'... Loading NGL library 'D:/Lattice/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... Loading NGL library 'D:/Lattice/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... All blocks are expanded and NGD expansion is successful. Writing NGD file Kurs11_impl1.ngd. ################### Begin Area Report (top)###################### Number of register bits => 24 of 1520 (1 % ) AND2 => 3 CCU2D => 3 FADD2B => 8 FD1S3AX => 16 FD1S3IX => 8 GSR => 1 IB => 9 LUT4 => 14 MULT2 => 6 OB => 8 OSCH => 1 ################### End Area Report ################## ################### Begin BlackBox Report ###################### TSALL => 1 ################### End BlackBox Report ################## ################### Begin Clock Report ###################### Clock Nets Number of Clocks: 1 Net : Clock, loads : 24 Clock Enable Nets Number of Clock Enables: 0 Top 0 highest fanout Clock Enables: Highest fanout non-clock nets Top 10 highest fanout non-clock nets: Net : Y_7_N_11_0, loads : 16 Net : Y_7_N_11_1, loads : 15 Net : A_sync_2, loads : 12 Net : A_sync_3, loads : 9 Net : Reset_N_10, loads : 8 Net : n476, loads : 7 Net : n475, loads : 7 Net : A_sync_4, loads : 6 Net : n210, loads : 6 Net : A_sync_5, loads : 4 ################### End Clock Report ################## Timing Report Summary -------------- -------------------------------------------------------------------------------- Constraint | Constraint| Actual|Levels -------------------------------------------------------------------------------- | | | create_clock -period 7.518000 -waveform | | | { 0.000000 3.759000 } -name Clock [ | | | get_nets { Clock } ] | 133.014 MHz| 103.402 MHz| 8 * | | | -------------------------------------------------------------------------------- 1 constraints not met. Peak Memory Usage: 56.168 MB -------------------------------------------------------------- Elapsed CPU time for LSE flow : 0.469 secs --------------------------------------------------------------