Lattice Synthesis Timing Report
--------------------------------------------------------------------------------
Lattice Synthesis Timing Report, Version  
Thu Mar 23 22:06:34 2023

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
------------------
Design:     top
Constraint file: top_temp_lse.sdc 
Report level:    verbose report, limited to 3 items per constraint
--------------------------------------------------------------------------------



================================================================================
Constraint: create_clock -period 7.518000 -waveform { 0.000000 3.759000 } -name Clock [ get_nets { Clock } ]
            2087 items scored, 1050 timing errors detected.
--------------------------------------------------------------------------------


Error:  The following path violates requirements by 2.153ns

 Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)

   Source:         FD1S3AX    CK             A_sync_i0  (from Clock +)
   Destination:    FD1S3IX    D              Temp__i8  (to Clock +)

   Delay:                   9.538ns  (33.8% logic, 66.2% route), 8 logic levels.

 Constraint Details:

      9.538ns data_path A_sync_i0 to Temp__i8 violates
      7.518ns delay constraint less
      0.133ns L_S requirement (totaling 7.385ns) by 2.153ns

 Path Details: A_sync_i0 to Temp__i8

   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
L_CO        ---     0.367             CK to Q              A_sync_i0 (from Clock)
Route        16   e 1.306                                  Y_7__N_11[0]
LUT4        ---     0.408              B to Z              i118_2_lut_rep_7
Route         7   e 1.049                                  n475
LUT4        ---     0.408                to                mult_6u_8u_0_mult_0_0
Route         1   e 0.660                                  mult_6u_8u_0_pp_0_2
LUT4        ---     0.408                to                Cadd_mult_6u_8u_0_0_1
Route         1   e 0.660                                  mult_6u_8u_0_pp_0_4
LUT4        ---     0.408                to                mult_6u_8u_0_add_0_2
Route         1   e 0.660                                  mult_6u_8u_0_pp_0_6
LUT4        ---     0.408                to                mult_6u_8u_0_add_0_3
Route         1   e 0.660                                  mult_6u_8u_0_pp_2_6
LUT4        ---     0.408                to                t_mult_6u_8u_0_add_1_2
Route         1   e 0.660                                  n69
A1_TO_F     ---     0.408           A[2] to S[2]           add_12_6
Route         1   e 0.660                                  Y_7__N_11[7]
                  --------
                    9.538  (33.8% logic, 66.2% route), 8 logic levels.


Error:  The following path violates requirements by 2.153ns

 Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)

   Source:         FD1S3AX    CK             A_sync_i0  (from Clock +)
   Destination:    FD1S3IX    D              Temp__i8  (to Clock +)

   Delay:                   9.538ns  (33.8% logic, 66.2% route), 8 logic levels.

 Constraint Details:

      9.538ns data_path A_sync_i0 to Temp__i8 violates
      7.518ns delay constraint less
      0.133ns L_S requirement (totaling 7.385ns) by 2.153ns

 Path Details: A_sync_i0 to Temp__i8

   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
L_CO        ---     0.367             CK to Q              A_sync_i0 (from Clock)
Route        16   e 1.306                                  Y_7__N_11[0]
LUT4        ---     0.408              B to Z              i118_2_lut_rep_7
Route         7   e 1.049                                  n475
LUT4        ---     0.408                to                mult_6u_8u_0_mult_0_0
Route         1   e 0.660                                  mult_6u_8u_0_pp_0_2
LUT4        ---     0.408                to                Cadd_mult_6u_8u_0_0_1
Route         1   e 0.660                                  mult_6u_8u_0_pp_0_4
LUT4        ---     0.408                to                mult_6u_8u_0_add_0_2
Route         1   e 0.660                                  mult_6u_8u_0_pp_0_6
LUT4        ---     0.408                to                mult_6u_8u_0_add_0_3
Route         1   e 0.660                                  mult_6u_8u_0_pp_2_6
LUT4        ---     0.408                to                t_mult_6u_8u_0_add_1_2
Route         1   e 0.660                                  n69
A1_TO_F     ---     0.408           A[2] to S[2]           add_12_6
Route         1   e 0.660                                  Y_7__N_11[7]
                  --------
                    9.538  (33.8% logic, 66.2% route), 8 logic levels.


Error:  The following path violates requirements by 2.153ns

 Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)

   Source:         FD1S3AX    CK             A_sync_i0  (from Clock +)
   Destination:    FD1S3IX    D              Temp__i8  (to Clock +)

   Delay:                   9.538ns  (33.8% logic, 66.2% route), 8 logic levels.

 Constraint Details:

      9.538ns data_path A_sync_i0 to Temp__i8 violates
      7.518ns delay constraint less
      0.133ns L_S requirement (totaling 7.385ns) by 2.153ns

 Path Details: A_sync_i0 to Temp__i8

   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
L_CO        ---     0.367             CK to Q              A_sync_i0 (from Clock)
Route        16   e 1.306                                  Y_7__N_11[0]
LUT4        ---     0.408              B to Z              i118_2_lut_rep_7
Route         7   e 1.049                                  n475
LUT4        ---     0.408                to                mult_6u_8u_0_mult_0_0
Route         1   e 0.660                                  n475
LUT4        ---     0.408                to                mult_6u_8u_0_mult_0_1
Route         1   e 0.660                                  n475
LUT4        ---     0.408                to                mult_6u_8u_0_mult_0_2
Route         1   e 0.660                                  mult_6u_8u_0_pp_0_6
LUT4        ---     0.408                to                mult_6u_8u_0_add_0_3
Route         1   e 0.660                                  mult_6u_8u_0_pp_2_6
LUT4        ---     0.408                to                t_mult_6u_8u_0_add_1_2
Route         1   e 0.660                                  n69
A1_TO_F     ---     0.408           A[2] to S[2]           add_12_6
Route         1   e 0.660                                  Y_7__N_11[7]
                  --------
                    9.538  (33.8% logic, 66.2% route), 8 logic levels.

Warning: 9.671 ns is the maximum delay for this constraint.


Timing Report Summary
--------------
--------------------------------------------------------------------------------
Constraint                              |   Constraint|       Actual|Levels
--------------------------------------------------------------------------------
                                        |             |             |
create_clock -period 7.518000 -waveform |             |             |
{ 0.000000 3.759000 } -name Clock [     |             |             |
get_nets { Clock } ]                    |     7.518 ns|     9.671 ns|     8 *
                                        |             |             |
--------------------------------------------------------------------------------


1 constraints not met.

--------------------------------------------------------------------------------
Critical Nets                           |   Loads|  Errors| % of total
--------------------------------------------------------------------------------
n475                                    |       7|     976|     92.95%
                                        |        |        |
mult_6u_8u_0_pp_2_6                     |       1|     902|     85.90%
                                        |        |        |
n69                                     |       1|     902|     85.90%
                                        |        |        |
mult_6u_8u_0_pp_0_4                     |       1|     588|     56.00%
                                        |        |        |
mult_6u_8u_0_pp_0_6                     |       1|     584|     55.62%
                                        |        |        |
Y_7__N_11[6]                            |       1|     507|     48.29%
                                        |        |        |
Y_7__N_11[7]                            |       1|     507|     48.29%
                                        |        |        |
Y_7__N_11[0]                            |      16|     454|     43.24%
                                        |        |        |
Y_7__N_11[1]                            |      15|     296|     28.19%
                                        |        |        |
mult_6u_8u_0_cin_lr_2                   |       1|     280|     26.67%
                                        |        |        |
mult_6u_8u_0_pp_2_4                     |       1|     236|     22.48%
                                        |        |        |
mult_6u_8u_0_cin_lr_4                   |       1|     152|     14.48%
                                        |        |        |
mult_6u_8u_0_pp_0_2                     |       1|     132|     12.57%
                                        |        |        |
A_sync[2]                               |      12|     126|     12.00%
                                        |        |        |
mco_3                                   |       1|     112|     10.67%
                                        |        |        |
--------------------------------------------------------------------------------


Timing summary:
---------------

Timing errors: 1050  Score: 1070868

Constraints cover  2087 paths, 57 nets, and 171 connections (85.5% coverage)


Peak memory: 58724352 bytes, TRCE: 1863680 bytes, DLYMAN: 0 bytes
CPU_TIME_REPORT: 0 secs