-------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 Mon Mar 20 22:03:45 2023 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Design file: top Device,speed: LCMXO2-1200HC,M Report level: verbose report, limited to 10 items per preference -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY NET "Clock" 133.014099 MHz ; 10 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 0.304ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q A_temp_i3 (from Clock +) Destination: FF Data in A_sync_i3 (to Clock +) Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. Constraint Details: 0.285ns physical path delay SLICE_29 to SLICE_6 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.304ns Physical Path Details: Data path SLICE_29 to SLICE_6: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R10C19C.CLK to R10C19C.Q0 SLICE_29 (from Clock) ROUTE 1 0.152 R10C19C.Q0 to R10C19A.M1 A_temp_3 (to Clock) -------- 0.285 (46.7% logic, 53.3% route), 1 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_29: Name Fanout Delay (ns) Site Resource ROUTE 12 1.216 OSC.OSC to R10C19C.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_6: Name Fanout Delay (ns) Site Resource ROUTE 12 1.216 OSC.OSC to R10C19A.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.304ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q A_temp_i7 (from Clock +) Destination: FF Data in A_sync_i7 (to Clock +) Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. Constraint Details: 0.285ns physical path delay SLICE_30 to SLICE_28 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.304ns Physical Path Details: Data path SLICE_30 to SLICE_28: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R8C18A.CLK to R8C18A.Q0 SLICE_30 (from Clock) ROUTE 1 0.152 R8C18A.Q0 to R8C18C.M0 A_temp_7 (to Clock) -------- 0.285 (46.7% logic, 53.3% route), 1 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_30: Name Fanout Delay (ns) Site Resource ROUTE 12 1.216 OSC.OSC to R8C18A.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_28: Name Fanout Delay (ns) Site Resource ROUTE 12 1.216 OSC.OSC to R8C18C.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.304ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q A_temp_i2 (from Clock +) Destination: FF Data in A_sync_i2 (to Clock +) Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. Constraint Details: 0.285ns physical path delay SLICE_32 to SLICE_6 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.304ns Physical Path Details: Data path SLICE_32 to SLICE_6: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R10C19D.CLK to R10C19D.Q1 SLICE_32 (from Clock) ROUTE 1 0.152 R10C19D.Q1 to R10C19A.M0 A_temp_2 (to Clock) -------- 0.285 (46.7% logic, 53.3% route), 1 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_32: Name Fanout Delay (ns) Site Resource ROUTE 12 1.216 OSC.OSC to R10C19D.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_6: Name Fanout Delay (ns) Site Resource ROUTE 12 1.216 OSC.OSC to R10C19A.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.306ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q A_temp_i5 (from Clock +) Destination: FF Data in A_sync_i5 (to Clock +) Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. Constraint Details: 0.287ns physical path delay SLICE_31 to SLICE_33 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.306ns Physical Path Details: Data path SLICE_31 to SLICE_33: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R8C20D.CLK to R8C20D.Q0 SLICE_31 (from Clock) ROUTE 1 0.154 R8C20D.Q0 to R8C19D.M0 A_temp_5 (to Clock) -------- 0.287 (46.3% logic, 53.7% route), 1 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_31: Name Fanout Delay (ns) Site Resource ROUTE 12 1.216 OSC.OSC to R8C20D.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_33: Name Fanout Delay (ns) Site Resource ROUTE 12 1.216 OSC.OSC to R8C19D.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.318ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q A_sync_i0 (from Clock +) Destination: FF Data in Temp_i1 (to Clock +) Delay: 0.299ns (44.5% logic, 55.5% route), 1 logic levels. Constraint Details: 0.299ns physical path delay SLICE_3 to SLICE_30 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.318ns Physical Path Details: Data path SLICE_3 to SLICE_30: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R8C19A.CLK to R8C19A.Q0 SLICE_3 (from Clock) ROUTE 15 0.166 R8C19A.Q0 to R8C18A.M1 Y_7_N_1_0 (to Clock) -------- 0.299 (44.5% logic, 55.5% route), 1 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 12 1.216 OSC.OSC to R8C19A.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_30: Name Fanout Delay (ns) Site Resource ROUTE 12 1.216 OSC.OSC to R8C18A.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.418ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q A_temp_i0 (from Clock +) Destination: FF Data in A_sync_i0 (to Clock +) Delay: 0.399ns (33.3% logic, 66.7% route), 1 logic levels. Constraint Details: 0.399ns physical path delay SLICE_28 to SLICE_3 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.418ns Physical Path Details: Data path SLICE_28 to SLICE_3: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R8C18C.CLK to R8C18C.Q1 SLICE_28 (from Clock) ROUTE 1 0.266 R8C18C.Q1 to R8C19A.M0 A_temp_0 (to Clock) -------- 0.399 (33.3% logic, 66.7% route), 1 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_28: Name Fanout Delay (ns) Site Resource ROUTE 12 1.216 OSC.OSC to R8C18C.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 12 1.216 OSC.OSC to R8C19A.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.418ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q A_temp_i4 (from Clock +) Destination: FF Data in A_sync_i4 (to Clock +) Delay: 0.399ns (33.3% logic, 66.7% route), 1 logic levels. Constraint Details: 0.399ns physical path delay SLICE_29 to SLICE_15 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.418ns Physical Path Details: Data path SLICE_29 to SLICE_15: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R10C19C.CLK to R10C19C.Q1 SLICE_29 (from Clock) ROUTE 1 0.266 R10C19C.Q1 to R9C19A.M0 A_temp_4 (to Clock) -------- 0.399 (33.3% logic, 66.7% route), 1 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_29: Name Fanout Delay (ns) Site Resource ROUTE 12 1.216 OSC.OSC to R10C19C.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_15: Name Fanout Delay (ns) Site Resource ROUTE 12 1.216 OSC.OSC to R9C19A.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.418ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q A_temp_i1 (from Clock +) Destination: FF Data in A_sync_i1 (to Clock +) Delay: 0.399ns (33.3% logic, 66.7% route), 1 logic levels. Constraint Details: 0.399ns physical path delay SLICE_32 to SLICE_3 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.418ns Physical Path Details: Data path SLICE_32 to SLICE_3: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R10C19D.CLK to R10C19D.Q0 SLICE_32 (from Clock) ROUTE 1 0.266 R10C19D.Q0 to R8C19A.M1 A_temp_1 (to Clock) -------- 0.399 (33.3% logic, 66.7% route), 1 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_32: Name Fanout Delay (ns) Site Resource ROUTE 12 1.216 OSC.OSC to R10C19D.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 12 1.216 OSC.OSC to R8C19A.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.461ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q A_sync_i5 (from Clock +) Destination: FF Data in Temp_i6 (to Clock +) Delay: 0.448ns (52.2% logic, 47.8% route), 2 logic levels. Constraint Details: 0.448ns physical path delay SLICE_33 to SLICE_14 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.461ns Physical Path Details: Data path SLICE_33 to SLICE_14: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R8C19D.CLK to R8C19D.Q0 SLICE_33 (from Clock) ROUTE 4 0.214 R8C19D.Q0 to R9C19B.A1 A_sync_5 CTOF_DEL --- 0.101 R9C19B.A1 to R9C19B.F1 SLICE_14 ROUTE 1 0.000 R9C19B.F1 to R9C19B.DI1 Y_7_N_1_5 (to Clock) -------- 0.448 (52.2% logic, 47.8% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_33: Name Fanout Delay (ns) Site Resource ROUTE 12 1.216 OSC.OSC to R8C19D.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_14: Name Fanout Delay (ns) Site Resource ROUTE 12 1.216 OSC.OSC to R9C19B.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.472ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q A_sync_i4 (from Clock +) Destination: FF Data in Temp_i5 (to Clock +) Delay: 0.459ns (51.0% logic, 49.0% route), 2 logic levels. Constraint Details: 0.459ns physical path delay SLICE_15 to SLICE_14 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.472ns Physical Path Details: Data path SLICE_15 to SLICE_14: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R9C19A.CLK to R9C19A.Q0 SLICE_15 (from Clock) ROUTE 6 0.225 R9C19A.Q0 to R9C19B.B0 A_sync_4 CTOF_DEL --- 0.101 R9C19B.B0 to R9C19B.F0 SLICE_14 ROUTE 1 0.000 R9C19B.F0 to R9C19B.DI0 Y_7_N_1_4 (to Clock) -------- 0.459 (51.0% logic, 49.0% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_15: Name Fanout Delay (ns) Site Resource ROUTE 12 1.216 OSC.OSC to R9C19A.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_14: Name Fanout Delay (ns) Site Resource ROUTE 12 1.216 OSC.OSC to R9C19B.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Report Summary -------------- ---------------------------------------------------------------------------- Preference(MIN Delays) | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY NET "Clock" 133.014099 MHz ; | 0.000 ns| 0.304 ns| 1 | | | ---------------------------------------------------------------------------- All preferences were met. Clock Domains Analysis ------------------------ Found 1 clocks: Clock Domain: Clock Source: OSCH_inst.OSC Loads: 12 Covered under: FREQUENCY NET "Clock" 133.014099 MHz ; Timing summary (Hold): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 616 paths, 1 nets, and 167 connections (95.43% coverage) Timing summary (Setup and Hold): --------------- Timing errors: 10 (setup), 0 (hold) Score: 7205 (setup), 0 (hold) Cumulative negative slack: 7205 (7205+0)