Place & Route TRACE Report

Loading design for application trce from file kurs12_statemachine.ncd.
Design name: top
NCD version: 3.3
Vendor:      LATTICE
Device:      LCMXO2-1200HC
Package:     TQFP100
Performance: 6
Loading device for application trce from file 'xo2c1200.nph' in environment: D:/Lattice/diamond/3.12/ispfpga.
Package Status:                     Final          Version 1.44.
Performance Hardware Data Status:   Final          Version 34.4.
Setup and Hold Report

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Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
Thu Mar 30 11:02:46 2023

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
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Command line:    trce -v 10 -gt -sethld -sp 6 -sphld m -o Kurs12_StateMachine.twr -gui -msgset D:/Lattice/Kurs12/promote.xml Kurs12_StateMachine.ncd Kurs12_StateMachine.prf 
Design file:     kurs12_statemachine.ncd
Preference file: kurs12_statemachine.prf
Device,speed:    LCMXO2-1200HC,6
Report level:    verbose report, limited to 10 items per preference
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Preference Summary

  • FREQUENCY NET "Clock" 14.000112 MHz (0 errors)
  • 1208 items scored, 0 timing errors detected. Report: 150.331MHz is the maximum frequency for this preference. BLOCK ASYNCPATHS BLOCK RESETPATHS BLOCK JTAG PATHS -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY NET "Clock" 14.000112 MHz ; 1208 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 64.776ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q MatrixKeyboard0/KeyCounter_i0_i1 (from Clock +) Destination: FF Data in MatrixKeyboard0/KeyCounter_i0_i2 (to Clock +) FF MatrixKeyboard0/KeyCounter_i0_i1 Delay: 6.429ns (36.0% logic, 64.0% route), 7 logic levels. Constraint Details: 6.429ns physical path delay MatrixKeyboard0/SLICE_42 to MatrixKeyboard0/SLICE_42 meets 71.428ns delay constraint less 0.000ns skew and 0.223ns LSR_SET requirement (totaling 71.205ns) by 64.776ns Physical Path Details: Data path MatrixKeyboard0/SLICE_42 to MatrixKeyboard0/SLICE_42: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.367 R8C12C.CLK to R8C12C.Q0 MatrixKeyboard0/SLICE_42 (from Clock) ROUTE 14 2.230 R8C12C.Q0 to R7C11A.M0 MatrixKeyboard0/KeyCounter_1 MTOOFX_DEL --- 0.313 R7C11A.M0 to R7C11A.OFX0 MatrixKeyboard0/i636/SLICE_55 ROUTE 1 0.000 R7C11A.OFX0 to R7C11A.FXB MatrixKeyboard0/n738 FXTOOFX_DE --- 0.205 R7C11A.FXB to R7C11A.OFX1 MatrixKeyboard0/i636/SLICE_55 ROUTE 1 0.000 R7C11A.OFX1 to R7C11B.FXB MatrixKeyboard0/n742 FXTOOFX_DE --- 0.205 R7C11B.FXB to R7C11B.OFX1 MatrixKeyboard0/i635/SLICE_54 ROUTE 3 0.621 R7C11B.OFX1 to R8C11B.C0 MatrixKeyboard0/n744 CTOF_DEL --- 0.408 R8C11B.C0 to R8C11B.F0 MatrixKeyboard0/SLICE_24 ROUTE 4 0.373 R8C11B.F0 to R8C11D.C0 MatrixKeyboard0/KeyPressed_N_186 CTOF_DEL --- 0.408 R8C11D.C0 to R8C11D.F0 MatrixKeyboard0/SLICE_67 ROUTE 4 0.366 R8C11D.F0 to R8C11D.C1 MatrixKeyboard0/Clock_enable_43 CTOF_DEL --- 0.408 R8C11D.C1 to R8C11D.F1 MatrixKeyboard0/SLICE_67 ROUTE 2 0.525 R8C11D.F1 to R8C12C.LSR MatrixKeyboard0/n417 (to Clock) -------- 6.429 (36.0% logic, 64.0% route), 7 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to MatrixKeyboard0/SLICE_42: Name Fanout Delay (ns) Site Resource ROUTE 48 2.809 OSC.OSC to R8C12C.CLK Clock -------- 2.809 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to MatrixKeyboard0/SLICE_42: Name Fanout Delay (ns) Site Resource ROUTE 48 2.809 OSC.OSC to R8C12C.CLK Clock -------- 2.809 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 64.776ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q MatrixKeyboard0/KeyCounter_i0_i1 (from Clock +) Destination: FF Data in MatrixKeyboard0/KeyCounter_i0_i4 (to Clock +) FF MatrixKeyboard0/KeyCounter_i0_i3 Delay: 6.429ns (36.0% logic, 64.0% route), 7 logic levels. Constraint Details: 6.429ns physical path delay MatrixKeyboard0/SLICE_42 to MatrixKeyboard0/SLICE_43 meets 71.428ns delay constraint less 0.000ns skew and 0.223ns LSR_SET requirement (totaling 71.205ns) by 64.776ns Physical Path Details: Data path MatrixKeyboard0/SLICE_42 to MatrixKeyboard0/SLICE_43: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.367 R8C12C.CLK to R8C12C.Q0 MatrixKeyboard0/SLICE_42 (from Clock) ROUTE 14 2.230 R8C12C.Q0 to R7C11A.M0 MatrixKeyboard0/KeyCounter_1 MTOOFX_DEL --- 0.313 R7C11A.M0 to R7C11A.OFX0 MatrixKeyboard0/i636/SLICE_55 ROUTE 1 0.000 R7C11A.OFX0 to R7C11A.FXB MatrixKeyboard0/n738 FXTOOFX_DE --- 0.205 R7C11A.FXB to R7C11A.OFX1 MatrixKeyboard0/i636/SLICE_55 ROUTE 1 0.000 R7C11A.OFX1 to R7C11B.FXB MatrixKeyboard0/n742 FXTOOFX_DE --- 0.205 R7C11B.FXB to R7C11B.OFX1 MatrixKeyboard0/i635/SLICE_54 ROUTE 3 0.621 R7C11B.OFX1 to R8C11B.C0 MatrixKeyboard0/n744 CTOF_DEL --- 0.408 R8C11B.C0 to R8C11B.F0 MatrixKeyboard0/SLICE_24 ROUTE 4 0.373 R8C11B.F0 to R8C11D.C0 MatrixKeyboard0/KeyPressed_N_186 CTOF_DEL --- 0.408 R8C11D.C0 to R8C11D.F0 MatrixKeyboard0/SLICE_67 ROUTE 4 0.366 R8C11D.F0 to R8C11D.C1 MatrixKeyboard0/Clock_enable_43 CTOF_DEL --- 0.408 R8C11D.C1 to R8C11D.F1 MatrixKeyboard0/SLICE_67 ROUTE 2 0.525 R8C11D.F1 to R8C12B.LSR MatrixKeyboard0/n417 (to Clock) -------- 6.429 (36.0% logic, 64.0% route), 7 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to MatrixKeyboard0/SLICE_42: Name Fanout Delay (ns) Site Resource ROUTE 48 2.809 OSC.OSC to R8C12C.CLK Clock -------- 2.809 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to MatrixKeyboard0/SLICE_43: Name Fanout Delay (ns) Site Resource ROUTE 48 2.809 OSC.OSC to R8C12B.CLK Clock -------- 2.809 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 65.131ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q MatrixKeyboard0/KeyCounter_i0_i1 (from Clock +) Destination: FF Data in MatrixKeyboard0/KeyCounter_i0_i2 (to Clock +) FF MatrixKeyboard0/KeyCounter_i0_i1 Delay: 6.074ns (38.1% logic, 61.9% route), 7 logic levels. Constraint Details: 6.074ns physical path delay MatrixKeyboard0/SLICE_42 to MatrixKeyboard0/SLICE_42 meets 71.428ns delay constraint less 0.000ns skew and 0.223ns LSR_SET requirement (totaling 71.205ns) by 65.131ns Physical Path Details: Data path MatrixKeyboard0/SLICE_42 to MatrixKeyboard0/SLICE_42: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.367 R8C12C.CLK to R8C12C.Q0 MatrixKeyboard0/SLICE_42 (from Clock) ROUTE 14 1.744 R8C12C.Q0 to R9C12C.M0 MatrixKeyboard0/KeyCounter_1 MTOOFX_DEL --- 0.313 R9C12C.M0 to R9C12C.OFX0 MatrixKeyboard0/i630/SLICE_49 ROUTE 1 0.000 R9C12C.OFX0 to R9C12C.FXB MatrixKeyboard0/n732 FXTOOFX_DE --- 0.205 R9C12C.FXB to R9C12C.OFX1 MatrixKeyboard0/i630/SLICE_49 ROUTE 1 0.000 R9C12C.OFX1 to R9C12B.FXA MatrixKeyboard0/n739 FXTOOFX_DE --- 0.205 R9C12B.FXA to R9C12B.OFX1 MatrixKeyboard0/i631/SLICE_50 ROUTE 3 0.752 R9C12B.OFX1 to R8C11B.D0 MatrixKeyboard0/n743 CTOF_DEL --- 0.408 R8C11B.D0 to R8C11B.F0 MatrixKeyboard0/SLICE_24 ROUTE 4 0.373 R8C11B.F0 to R8C11D.C0 MatrixKeyboard0/KeyPressed_N_186 CTOF_DEL --- 0.408 R8C11D.C0 to R8C11D.F0 MatrixKeyboard0/SLICE_67 ROUTE 4 0.366 R8C11D.F0 to R8C11D.C1 MatrixKeyboard0/Clock_enable_43 CTOF_DEL --- 0.408 R8C11D.C1 to R8C11D.F1 MatrixKeyboard0/SLICE_67 ROUTE 2 0.525 R8C11D.F1 to R8C12C.LSR MatrixKeyboard0/n417 (to Clock) -------- 6.074 (38.1% logic, 61.9% route), 7 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to MatrixKeyboard0/SLICE_42: Name Fanout Delay (ns) Site Resource ROUTE 48 2.809 OSC.OSC to R8C12C.CLK Clock -------- 2.809 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to MatrixKeyboard0/SLICE_42: Name Fanout Delay (ns) Site Resource ROUTE 48 2.809 OSC.OSC to R8C12C.CLK Clock -------- 2.809 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 65.131ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q MatrixKeyboard0/KeyCounter_i0_i1 (from Clock +) Destination: FF Data in MatrixKeyboard0/KeyCounter_i0_i4 (to Clock +) FF MatrixKeyboard0/KeyCounter_i0_i3 Delay: 6.074ns (38.1% logic, 61.9% route), 7 logic levels. Constraint Details: 6.074ns physical path delay MatrixKeyboard0/SLICE_42 to MatrixKeyboard0/SLICE_43 meets 71.428ns delay constraint less 0.000ns skew and 0.223ns LSR_SET requirement (totaling 71.205ns) by 65.131ns Physical Path Details: Data path MatrixKeyboard0/SLICE_42 to MatrixKeyboard0/SLICE_43: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.367 R8C12C.CLK to R8C12C.Q0 MatrixKeyboard0/SLICE_42 (from Clock) ROUTE 14 1.744 R8C12C.Q0 to R9C12C.M0 MatrixKeyboard0/KeyCounter_1 MTOOFX_DEL --- 0.313 R9C12C.M0 to R9C12C.OFX0 MatrixKeyboard0/i630/SLICE_49 ROUTE 1 0.000 R9C12C.OFX0 to R9C12C.FXB MatrixKeyboard0/n732 FXTOOFX_DE --- 0.205 R9C12C.FXB to R9C12C.OFX1 MatrixKeyboard0/i630/SLICE_49 ROUTE 1 0.000 R9C12C.OFX1 to R9C12B.FXA MatrixKeyboard0/n739 FXTOOFX_DE --- 0.205 R9C12B.FXA to R9C12B.OFX1 MatrixKeyboard0/i631/SLICE_50 ROUTE 3 0.752 R9C12B.OFX1 to R8C11B.D0 MatrixKeyboard0/n743 CTOF_DEL --- 0.408 R8C11B.D0 to R8C11B.F0 MatrixKeyboard0/SLICE_24 ROUTE 4 0.373 R8C11B.F0 to R8C11D.C0 MatrixKeyboard0/KeyPressed_N_186 CTOF_DEL --- 0.408 R8C11D.C0 to R8C11D.F0 MatrixKeyboard0/SLICE_67 ROUTE 4 0.366 R8C11D.F0 to R8C11D.C1 MatrixKeyboard0/Clock_enable_43 CTOF_DEL --- 0.408 R8C11D.C1 to R8C11D.F1 MatrixKeyboard0/SLICE_67 ROUTE 2 0.525 R8C11D.F1 to R8C12B.LSR MatrixKeyboard0/n417 (to Clock) -------- 6.074 (38.1% logic, 61.9% route), 7 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to MatrixKeyboard0/SLICE_42: Name Fanout Delay (ns) Site Resource ROUTE 48 2.809 OSC.OSC to R8C12C.CLK Clock -------- 2.809 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to MatrixKeyboard0/SLICE_43: Name Fanout Delay (ns) Site Resource ROUTE 48 2.809 OSC.OSC to R8C12B.CLK Clock -------- 2.809 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 65.218ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q MatrixKeyboard0/KeyCounter_i0_i1 (from Clock +) Destination: FF Data in MatrixKeyboard0/State_FSM_i2 (to Clock +) Delay: 6.077ns (31.4% logic, 68.6% route), 6 logic levels. Constraint Details: 6.077ns physical path delay MatrixKeyboard0/SLICE_42 to MatrixKeyboard0/SLICE_45 meets 71.428ns delay constraint less 0.000ns skew and 0.133ns DIN_SET requirement (totaling 71.295ns) by 65.218ns Physical Path Details: Data path MatrixKeyboard0/SLICE_42 to MatrixKeyboard0/SLICE_45: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.367 R8C12C.CLK to R8C12C.Q0 MatrixKeyboard0/SLICE_42 (from Clock) ROUTE 14 2.230 R8C12C.Q0 to R7C11A.M0 MatrixKeyboard0/KeyCounter_1 MTOOFX_DEL --- 0.313 R7C11A.M0 to R7C11A.OFX0 MatrixKeyboard0/i636/SLICE_55 ROUTE 1 0.000 R7C11A.OFX0 to R7C11A.FXB MatrixKeyboard0/n738 FXTOOFX_DE --- 0.205 R7C11A.FXB to R7C11A.OFX1 MatrixKeyboard0/i636/SLICE_55 ROUTE 1 0.000 R7C11A.OFX1 to R7C11B.FXB MatrixKeyboard0/n742 FXTOOFX_DE --- 0.205 R7C11B.FXB to R7C11B.OFX1 MatrixKeyboard0/i635/SLICE_54 ROUTE 3 1.158 R7C11B.OFX1 to R8C12D.B1 MatrixKeyboard0/n744 CTOF_DEL --- 0.408 R8C12D.B1 to R8C12D.F1 MatrixKeyboard0/SLICE_66 ROUTE 1 0.783 R8C12D.F1 to R8C11C.B0 MatrixKeyboard0/n834 CTOF_DEL --- 0.408 R8C11C.B0 to R8C11C.F0 MatrixKeyboard0/SLICE_45 ROUTE 1 0.000 R8C11C.F0 to R8C11C.DI0 MatrixKeyboard0/n335 (to Clock) -------- 6.077 (31.4% logic, 68.6% route), 6 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to MatrixKeyboard0/SLICE_42: Name Fanout Delay (ns) Site Resource ROUTE 48 2.809 OSC.OSC to R8C12C.CLK Clock -------- 2.809 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to MatrixKeyboard0/SLICE_45: Name Fanout Delay (ns) Site Resource ROUTE 48 2.809 OSC.OSC to R8C11C.CLK Clock -------- 2.809 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 65.228ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q MatrixKeyboard0/KeyCounter_i0_i1 (from Clock +) Destination: FF Data in MatrixKeyboard0/KeyCounter_i0_i2 (to Clock +) FF MatrixKeyboard0/KeyCounter_i0_i1 Delay: 5.983ns (31.9% logic, 68.1% route), 6 logic levels. Constraint Details: 5.983ns physical path delay MatrixKeyboard0/SLICE_42 to MatrixKeyboard0/SLICE_42 meets 71.428ns delay constraint less 0.000ns skew and 0.217ns CE_SET requirement (totaling 71.211ns) by 65.228ns Physical Path Details: Data path MatrixKeyboard0/SLICE_42 to MatrixKeyboard0/SLICE_42: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.367 R8C12C.CLK to R8C12C.Q0 MatrixKeyboard0/SLICE_42 (from Clock) ROUTE 14 2.230 R8C12C.Q0 to R7C11A.M0 MatrixKeyboard0/KeyCounter_1 MTOOFX_DEL --- 0.313 R7C11A.M0 to R7C11A.OFX0 MatrixKeyboard0/i636/SLICE_55 ROUTE 1 0.000 R7C11A.OFX0 to R7C11A.FXB MatrixKeyboard0/n738 FXTOOFX_DE --- 0.205 R7C11A.FXB to R7C11A.OFX1 MatrixKeyboard0/i636/SLICE_55 ROUTE 1 0.000 R7C11A.OFX1 to R7C11B.FXB MatrixKeyboard0/n742 FXTOOFX_DE --- 0.205 R7C11B.FXB to R7C11B.OFX1 MatrixKeyboard0/i635/SLICE_54 ROUTE 3 0.621 R7C11B.OFX1 to R8C11B.C0 MatrixKeyboard0/n744 CTOF_DEL --- 0.408 R8C11B.C0 to R8C11B.F0 MatrixKeyboard0/SLICE_24 ROUTE 4 0.373 R8C11B.F0 to R8C11D.C0 MatrixKeyboard0/KeyPressed_N_186 CTOF_DEL --- 0.408 R8C11D.C0 to R8C11D.F0 MatrixKeyboard0/SLICE_67 ROUTE 4 0.853 R8C11D.F0 to R8C12C.CE MatrixKeyboard0/Clock_enable_43 (to Clock) -------- 5.983 (31.9% logic, 68.1% route), 6 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to MatrixKeyboard0/SLICE_42: Name Fanout Delay (ns) Site Resource ROUTE 48 2.809 OSC.OSC to R8C12C.CLK Clock -------- 2.809 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to MatrixKeyboard0/SLICE_42: Name Fanout Delay (ns) Site Resource ROUTE 48 2.809 OSC.OSC to R8C12C.CLK Clock -------- 2.809 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 65.228ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q MatrixKeyboard0/KeyCounter_i0_i1 (from Clock +) Destination: FF Data in MatrixKeyboard0/KeyCounter_i0_i4 (to Clock +) FF MatrixKeyboard0/KeyCounter_i0_i3 Delay: 5.983ns (31.9% logic, 68.1% route), 6 logic levels. Constraint Details: 5.983ns physical path delay MatrixKeyboard0/SLICE_42 to MatrixKeyboard0/SLICE_43 meets 71.428ns delay constraint less 0.000ns skew and 0.217ns CE_SET requirement (totaling 71.211ns) by 65.228ns Physical Path Details: Data path MatrixKeyboard0/SLICE_42 to MatrixKeyboard0/SLICE_43: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.367 R8C12C.CLK to R8C12C.Q0 MatrixKeyboard0/SLICE_42 (from Clock) ROUTE 14 2.230 R8C12C.Q0 to R7C11A.M0 MatrixKeyboard0/KeyCounter_1 MTOOFX_DEL --- 0.313 R7C11A.M0 to R7C11A.OFX0 MatrixKeyboard0/i636/SLICE_55 ROUTE 1 0.000 R7C11A.OFX0 to R7C11A.FXB MatrixKeyboard0/n738 FXTOOFX_DE --- 0.205 R7C11A.FXB to R7C11A.OFX1 MatrixKeyboard0/i636/SLICE_55 ROUTE 1 0.000 R7C11A.OFX1 to R7C11B.FXB MatrixKeyboard0/n742 FXTOOFX_DE --- 0.205 R7C11B.FXB to R7C11B.OFX1 MatrixKeyboard0/i635/SLICE_54 ROUTE 3 0.621 R7C11B.OFX1 to R8C11B.C0 MatrixKeyboard0/n744 CTOF_DEL --- 0.408 R8C11B.C0 to R8C11B.F0 MatrixKeyboard0/SLICE_24 ROUTE 4 0.373 R8C11B.F0 to R8C11D.C0 MatrixKeyboard0/KeyPressed_N_186 CTOF_DEL --- 0.408 R8C11D.C0 to R8C11D.F0 MatrixKeyboard0/SLICE_67 ROUTE 4 0.853 R8C11D.F0 to R8C12B.CE MatrixKeyboard0/Clock_enable_43 (to Clock) -------- 5.983 (31.9% logic, 68.1% route), 6 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to MatrixKeyboard0/SLICE_42: Name Fanout Delay (ns) Site Resource ROUTE 48 2.809 OSC.OSC to R8C12C.CLK Clock -------- 2.809 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to MatrixKeyboard0/SLICE_43: Name Fanout Delay (ns) Site Resource ROUTE 48 2.809 OSC.OSC to R8C12B.CLK Clock -------- 2.809 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 65.424ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q MatrixKeyboard0/KeyCounter_i0_i0 (from Clock +) Destination: FF Data in MatrixKeyboard0/KeyCounter_i0_i4 (to Clock +) FF MatrixKeyboard0/KeyCounter_i0_i3 Delay: 5.781ns (45.0% logic, 55.0% route), 7 logic levels. Constraint Details: 5.781ns physical path delay MatrixKeyboard0/SLICE_41 to MatrixKeyboard0/SLICE_43 meets 71.428ns delay constraint less 0.000ns skew and 0.223ns LSR_SET requirement (totaling 71.205ns) by 65.424ns Physical Path Details: Data path MatrixKeyboard0/SLICE_41 to MatrixKeyboard0/SLICE_43: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.367 R8C11A.CLK to R8C11A.Q0 MatrixKeyboard0/SLICE_41 (from Clock) ROUTE 23 1.163 R8C11A.Q0 to R9C12D.B0 MatrixKeyboard0/KeyCounter_0 CTOOFX_DEL --- 0.601 R9C12D.B0 to R9C12D.OFX0 MatrixKeyboard0/i629/SLICE_48 ROUTE 1 0.000 R9C12D.OFX0 to R9C12C.FXA MatrixKeyboard0/n731 FXTOOFX_DE --- 0.205 R9C12C.FXA to R9C12C.OFX1 MatrixKeyboard0/i630/SLICE_49 ROUTE 1 0.000 R9C12C.OFX1 to R9C12B.FXA MatrixKeyboard0/n739 FXTOOFX_DE --- 0.205 R9C12B.FXA to R9C12B.OFX1 MatrixKeyboard0/i631/SLICE_50 ROUTE 3 0.752 R9C12B.OFX1 to R8C11B.D0 MatrixKeyboard0/n743 CTOF_DEL --- 0.408 R8C11B.D0 to R8C11B.F0 MatrixKeyboard0/SLICE_24 ROUTE 4 0.373 R8C11B.F0 to R8C11D.C0 MatrixKeyboard0/KeyPressed_N_186 CTOF_DEL --- 0.408 R8C11D.C0 to R8C11D.F0 MatrixKeyboard0/SLICE_67 ROUTE 4 0.366 R8C11D.F0 to R8C11D.C1 MatrixKeyboard0/Clock_enable_43 CTOF_DEL --- 0.408 R8C11D.C1 to R8C11D.F1 MatrixKeyboard0/SLICE_67 ROUTE 2 0.525 R8C11D.F1 to R8C12B.LSR MatrixKeyboard0/n417 (to Clock) -------- 5.781 (45.0% logic, 55.0% route), 7 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to MatrixKeyboard0/SLICE_41: Name Fanout Delay (ns) Site Resource ROUTE 48 2.809 OSC.OSC to R8C11A.CLK Clock -------- 2.809 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to MatrixKeyboard0/SLICE_43: Name Fanout Delay (ns) Site Resource ROUTE 48 2.809 OSC.OSC to R8C12B.CLK Clock -------- 2.809 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 65.424ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q MatrixKeyboard0/KeyCounter_i0_i0 (from Clock +) Destination: FF Data in MatrixKeyboard0/KeyCounter_i0_i2 (to Clock +) FF MatrixKeyboard0/KeyCounter_i0_i1 Delay: 5.781ns (45.0% logic, 55.0% route), 7 logic levels. Constraint Details: 5.781ns physical path delay MatrixKeyboard0/SLICE_41 to MatrixKeyboard0/SLICE_42 meets 71.428ns delay constraint less 0.000ns skew and 0.223ns LSR_SET requirement (totaling 71.205ns) by 65.424ns Physical Path Details: Data path MatrixKeyboard0/SLICE_41 to MatrixKeyboard0/SLICE_42: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.367 R8C11A.CLK to R8C11A.Q0 MatrixKeyboard0/SLICE_41 (from Clock) ROUTE 23 1.163 R8C11A.Q0 to R9C12D.B0 MatrixKeyboard0/KeyCounter_0 CTOOFX_DEL --- 0.601 R9C12D.B0 to R9C12D.OFX0 MatrixKeyboard0/i629/SLICE_48 ROUTE 1 0.000 R9C12D.OFX0 to R9C12C.FXA MatrixKeyboard0/n731 FXTOOFX_DE --- 0.205 R9C12C.FXA to R9C12C.OFX1 MatrixKeyboard0/i630/SLICE_49 ROUTE 1 0.000 R9C12C.OFX1 to R9C12B.FXA MatrixKeyboard0/n739 FXTOOFX_DE --- 0.205 R9C12B.FXA to R9C12B.OFX1 MatrixKeyboard0/i631/SLICE_50 ROUTE 3 0.752 R9C12B.OFX1 to R8C11B.D0 MatrixKeyboard0/n743 CTOF_DEL --- 0.408 R8C11B.D0 to R8C11B.F0 MatrixKeyboard0/SLICE_24 ROUTE 4 0.373 R8C11B.F0 to R8C11D.C0 MatrixKeyboard0/KeyPressed_N_186 CTOF_DEL --- 0.408 R8C11D.C0 to R8C11D.F0 MatrixKeyboard0/SLICE_67 ROUTE 4 0.366 R8C11D.F0 to R8C11D.C1 MatrixKeyboard0/Clock_enable_43 CTOF_DEL --- 0.408 R8C11D.C1 to R8C11D.F1 MatrixKeyboard0/SLICE_67 ROUTE 2 0.525 R8C11D.F1 to R8C12C.LSR MatrixKeyboard0/n417 (to Clock) -------- 5.781 (45.0% logic, 55.0% route), 7 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to MatrixKeyboard0/SLICE_41: Name Fanout Delay (ns) Site Resource ROUTE 48 2.809 OSC.OSC to R8C11A.CLK Clock -------- 2.809 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to MatrixKeyboard0/SLICE_42: Name Fanout Delay (ns) Site Resource ROUTE 48 2.809 OSC.OSC to R8C12C.CLK Clock -------- 2.809 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 65.424ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q MatrixKeyboard0/KeyCounter_i0_i0 (from Clock +) Destination: FF Data in MatrixKeyboard0/KeyCounter_i0_i2 (to Clock +) FF MatrixKeyboard0/KeyCounter_i0_i1 Delay: 5.781ns (45.0% logic, 55.0% route), 7 logic levels. Constraint Details: 5.781ns physical path delay MatrixKeyboard0/SLICE_41 to MatrixKeyboard0/SLICE_42 meets 71.428ns delay constraint less 0.000ns skew and 0.223ns LSR_SET requirement (totaling 71.205ns) by 65.424ns Physical Path Details: Data path MatrixKeyboard0/SLICE_41 to MatrixKeyboard0/SLICE_42: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.367 R8C11A.CLK to R8C11A.Q0 MatrixKeyboard0/SLICE_41 (from Clock) ROUTE 23 1.163 R8C11A.Q0 to R9C12D.B1 MatrixKeyboard0/KeyCounter_0 CTOOFX_DEL --- 0.601 R9C12D.B1 to R9C12D.OFX0 MatrixKeyboard0/i629/SLICE_48 ROUTE 1 0.000 R9C12D.OFX0 to R9C12C.FXA MatrixKeyboard0/n731 FXTOOFX_DE --- 0.205 R9C12C.FXA to R9C12C.OFX1 MatrixKeyboard0/i630/SLICE_49 ROUTE 1 0.000 R9C12C.OFX1 to R9C12B.FXA MatrixKeyboard0/n739 FXTOOFX_DE --- 0.205 R9C12B.FXA to R9C12B.OFX1 MatrixKeyboard0/i631/SLICE_50 ROUTE 3 0.752 R9C12B.OFX1 to R8C11B.D0 MatrixKeyboard0/n743 CTOF_DEL --- 0.408 R8C11B.D0 to R8C11B.F0 MatrixKeyboard0/SLICE_24 ROUTE 4 0.373 R8C11B.F0 to R8C11D.C0 MatrixKeyboard0/KeyPressed_N_186 CTOF_DEL --- 0.408 R8C11D.C0 to R8C11D.F0 MatrixKeyboard0/SLICE_67 ROUTE 4 0.366 R8C11D.F0 to R8C11D.C1 MatrixKeyboard0/Clock_enable_43 CTOF_DEL --- 0.408 R8C11D.C1 to R8C11D.F1 MatrixKeyboard0/SLICE_67 ROUTE 2 0.525 R8C11D.F1 to R8C12C.LSR MatrixKeyboard0/n417 (to Clock) -------- 5.781 (45.0% logic, 55.0% route), 7 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to MatrixKeyboard0/SLICE_41: Name Fanout Delay (ns) Site Resource ROUTE 48 2.809 OSC.OSC to R8C11A.CLK Clock -------- 2.809 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to MatrixKeyboard0/SLICE_42: Name Fanout Delay (ns) Site Resource ROUTE 48 2.809 OSC.OSC to R8C12C.CLK Clock -------- 2.809 (0.0% logic, 100.0% route), 0 logic levels. Report: 150.331MHz is the maximum frequency for this preference. Report Summary -------------- ---------------------------------------------------------------------------- Preference | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY NET "Clock" 14.000112 MHz ; | 14.000 MHz| 150.331 MHz| 7 | | | ---------------------------------------------------------------------------- All preferences were met. Clock Domains Analysis ------------------------ Found 1 clocks: Clock Domain: Clock Source: OSCH_inst.OSC Loads: 48 Covered under: FREQUENCY NET "Clock" 14.000112 MHz ; Timing summary (Setup): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 1208 paths, 1 nets, and 535 connections (94.36% coverage) -------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 Thu Mar 30 11:02:46 2023 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Command line: trce -v 10 -gt -sethld -sp 6 -sphld m -o Kurs12_StateMachine.twr -gui -msgset D:/Lattice/Kurs12/promote.xml Kurs12_StateMachine.ncd Kurs12_StateMachine.prf Design file: kurs12_statemachine.ncd Preference file: kurs12_statemachine.prf Device,speed: LCMXO2-1200HC,m Report level: verbose report, limited to 10 items per preference -------------------------------------------------------------------------------- Preference Summary
  • FREQUENCY NET "Clock" 14.000112 MHz (0 errors)
  • 1208 items scored, 0 timing errors detected. BLOCK ASYNCPATHS BLOCK RESETPATHS BLOCK JTAG PATHS -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY NET "Clock" 14.000112 MHz ; 1208 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 0.306ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q Data_i0_i0 (from Clock +) Destination: FF Data in Data_i0_i5 (to Clock +) Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. Constraint Details: 0.287ns physical path delay SLICE_73 to SLICE_74 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.306ns Physical Path Details: Data path SLICE_73 to SLICE_74: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R10C10B.CLK to R10C10B.Q0 SLICE_73 (from Clock) ROUTE 2 0.154 R10C10B.Q0 to R10C10A.M1 Data_0 (to Clock) -------- 0.287 (46.3% logic, 53.7% route), 1 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_73: Name Fanout Delay (ns) Site Resource ROUTE 48 1.216 OSC.OSC to R10C10B.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_74: Name Fanout Delay (ns) Site Resource ROUTE 48 1.216 OSC.OSC to R10C10A.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.307ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q Data_i0_i5 (from Clock +) Destination: FF Data in Data_i0_i10 (to Clock +) Delay: 0.288ns (46.2% logic, 53.8% route), 1 logic levels. Constraint Details: 0.288ns physical path delay SLICE_74 to SLICE_72 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.307ns Physical Path Details: Data path SLICE_74 to SLICE_72: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R10C10A.CLK to R10C10A.Q1 SLICE_74 (from Clock) ROUTE 3 0.155 R10C10A.Q1 to R10C10C.M0 Data_5 (to Clock) -------- 0.288 (46.2% logic, 53.8% route), 1 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_74: Name Fanout Delay (ns) Site Resource ROUTE 48 1.216 OSC.OSC to R10C10A.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_72: Name Fanout Delay (ns) Site Resource ROUTE 48 1.216 OSC.OSC to R10C10C.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.308ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q Data_i0_i6 (from Clock +) Destination: FF Data in Data_i0_i11 (to Clock +) Delay: 0.289ns (46.0% logic, 54.0% route), 1 logic levels. Constraint Details: 0.289ns physical path delay SLICE_75 to SLICE_72 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.308ns Physical Path Details: Data path SLICE_75 to SLICE_72: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R8C10C.CLK to R8C10C.Q0 SLICE_75 (from Clock) ROUTE 3 0.156 R8C10C.Q0 to R10C10C.M1 Data_6 (to Clock) -------- 0.289 (46.0% logic, 54.0% route), 1 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_75: Name Fanout Delay (ns) Site Resource ROUTE 48 1.216 OSC.OSC to R8C10C.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_72: Name Fanout Delay (ns) Site Resource ROUTE 48 1.216 OSC.OSC to R10C10C.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.308ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q Data_i0_i2 (from Clock +) Destination: FF Data in Data_i0_i7 (to Clock +) Delay: 0.289ns (46.0% logic, 54.0% route), 1 logic levels. Constraint Details: 0.289ns physical path delay SLICE_77 to SLICE_75 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.308ns Physical Path Details: Data path SLICE_77 to SLICE_75: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R9C10C.CLK to R9C10C.Q0 SLICE_77 (from Clock) ROUTE 2 0.156 R9C10C.Q0 to R8C10C.M1 Data_2 (to Clock) -------- 0.289 (46.0% logic, 54.0% route), 1 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_77: Name Fanout Delay (ns) Site Resource ROUTE 48 1.216 OSC.OSC to R9C10C.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_75: Name Fanout Delay (ns) Site Resource ROUTE 48 1.216 OSC.OSC to R8C10C.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.311ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q Data_i0_i10 (from Clock +) Destination: FF Data in Data_i0_i15 (to Clock +) Delay: 0.292ns (45.5% logic, 54.5% route), 1 logic levels. Constraint Details: 0.292ns physical path delay SLICE_72 to SLICE_82 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.311ns Physical Path Details: Data path SLICE_72 to SLICE_82: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R10C10C.CLK to R10C10C.Q0 SLICE_72 (from Clock) ROUTE 3 0.159 R10C10C.Q0 to R10C9C.M1 Data_10 (to Clock) -------- 0.292 (45.5% logic, 54.5% route), 1 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_72: Name Fanout Delay (ns) Site Resource ROUTE 48 1.216 OSC.OSC to R10C10C.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_82: Name Fanout Delay (ns) Site Resource ROUTE 48 1.216 OSC.OSC to R10C9C.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DisplayMultiplex0/StrobeGenerator0/Counter_i0 (from Clock +) Destination: FF Data in DisplayMultiplex0/StrobeGenerator0/Counter_i0 (to Clock +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay DisplayMultiplex0/StrobeGenerator0/SLICE_2 to DisplayMultiplex0/StrobeGenerator0/SLICE_2 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path DisplayMultiplex0/StrobeGenerator0/SLICE_2 to DisplayMultiplex0/StrobeGenerator0/SLICE_2: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R7C7A.CLK to R7C7A.Q1 DisplayMultiplex0/StrobeGenerator0/SLICE_2 (from Clock) ROUTE 2 0.132 R7C7A.Q1 to R7C7A.A1 DisplayMultiplex0/StrobeGenerator0/Counter_0 CTOF_DEL --- 0.101 R7C7A.A1 to R7C7A.F1 DisplayMultiplex0/StrobeGenerator0/SLICE_2 ROUTE 1 0.000 R7C7A.F1 to R7C7A.DI1 DisplayMultiplex0/StrobeGenerator0/Counter_14_N_60_0 (to Clock) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to DisplayMultiplex0/StrobeGenerator0/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 48 1.216 OSC.OSC to R7C7A.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to DisplayMultiplex0/StrobeGenerator0/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 48 1.216 OSC.OSC to R7C7A.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DisplayMultiplex0/StrobeGenerator0/Counter_i1 (from Clock +) Destination: FF Data in DisplayMultiplex0/StrobeGenerator0/Counter_i1 (to Clock +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay DisplayMultiplex0/StrobeGenerator0/SLICE_5 to DisplayMultiplex0/StrobeGenerator0/SLICE_5 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path DisplayMultiplex0/StrobeGenerator0/SLICE_5 to DisplayMultiplex0/StrobeGenerator0/SLICE_5: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R7C7B.CLK to R7C7B.Q0 DisplayMultiplex0/StrobeGenerator0/SLICE_5 (from Clock) ROUTE 2 0.132 R7C7B.Q0 to R7C7B.A0 DisplayMultiplex0/StrobeGenerator0/Counter_1 CTOF_DEL --- 0.101 R7C7B.A0 to R7C7B.F0 DisplayMultiplex0/StrobeGenerator0/SLICE_5 ROUTE 1 0.000 R7C7B.F0 to R7C7B.DI0 DisplayMultiplex0/StrobeGenerator0/Counter_14_N_60_1 (to Clock) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to DisplayMultiplex0/StrobeGenerator0/SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 48 1.216 OSC.OSC to R7C7B.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to DisplayMultiplex0/StrobeGenerator0/SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 48 1.216 OSC.OSC to R7C7B.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DisplayMultiplex0/StrobeGenerator0/Counter_i7 (from Clock +) Destination: FF Data in DisplayMultiplex0/StrobeGenerator0/Counter_i7 (to Clock +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay DisplayMultiplex0/StrobeGenerator0/SLICE_3 to DisplayMultiplex0/StrobeGenerator0/SLICE_3 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path DisplayMultiplex0/StrobeGenerator0/SLICE_3 to DisplayMultiplex0/StrobeGenerator0/SLICE_3: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R7C8A.CLK to R7C8A.Q0 DisplayMultiplex0/StrobeGenerator0/SLICE_3 (from Clock) ROUTE 2 0.132 R7C8A.Q0 to R7C8A.A0 DisplayMultiplex0/StrobeGenerator0/Counter_7 CTOF_DEL --- 0.101 R7C8A.A0 to R7C8A.F0 DisplayMultiplex0/StrobeGenerator0/SLICE_3 ROUTE 1 0.000 R7C8A.F0 to R7C8A.DI0 DisplayMultiplex0/StrobeGenerator0/Counter_14_N_60_7 (to Clock) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to DisplayMultiplex0/StrobeGenerator0/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 48 1.216 OSC.OSC to R7C8A.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to DisplayMultiplex0/StrobeGenerator0/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 48 1.216 OSC.OSC to R7C8A.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DisplayMultiplex0/StrobeGenerator0/Counter_i9 (from Clock +) Destination: FF Data in DisplayMultiplex0/StrobeGenerator0/Counter_i9 (to Clock +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay DisplayMultiplex0/StrobeGenerator0/SLICE_4 to DisplayMultiplex0/StrobeGenerator0/SLICE_4 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path DisplayMultiplex0/StrobeGenerator0/SLICE_4 to DisplayMultiplex0/StrobeGenerator0/SLICE_4: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R7C8B.CLK to R7C8B.Q0 DisplayMultiplex0/StrobeGenerator0/SLICE_4 (from Clock) ROUTE 2 0.132 R7C8B.Q0 to R7C8B.A0 DisplayMultiplex0/StrobeGenerator0/Counter_9 CTOF_DEL --- 0.101 R7C8B.A0 to R7C8B.F0 DisplayMultiplex0/StrobeGenerator0/SLICE_4 ROUTE 1 0.000 R7C8B.F0 to R7C8B.DI0 DisplayMultiplex0/StrobeGenerator0/Counter_14_N_60_9 (to Clock) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to DisplayMultiplex0/StrobeGenerator0/SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 48 1.216 OSC.OSC to R7C8B.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to DisplayMultiplex0/StrobeGenerator0/SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 48 1.216 OSC.OSC to R7C8B.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DisplayMultiplex0/StrobeGenerator0/Counter_i4 (from Clock +) Destination: FF Data in DisplayMultiplex0/StrobeGenerator0/Counter_i4 (to Clock +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay DisplayMultiplex0/StrobeGenerator0/SLICE_0 to DisplayMultiplex0/StrobeGenerator0/SLICE_0 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path DisplayMultiplex0/StrobeGenerator0/SLICE_0 to DisplayMultiplex0/StrobeGenerator0/SLICE_0: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R7C7C.CLK to R7C7C.Q1 DisplayMultiplex0/StrobeGenerator0/SLICE_0 (from Clock) ROUTE 2 0.132 R7C7C.Q1 to R7C7C.A1 DisplayMultiplex0/StrobeGenerator0/Counter_4 CTOF_DEL --- 0.101 R7C7C.A1 to R7C7C.F1 DisplayMultiplex0/StrobeGenerator0/SLICE_0 ROUTE 1 0.000 R7C7C.F1 to R7C7C.DI1 DisplayMultiplex0/StrobeGenerator0/Counter_14_N_60_4 (to Clock) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to DisplayMultiplex0/StrobeGenerator0/SLICE_0: Name Fanout Delay (ns) Site Resource ROUTE 48 1.216 OSC.OSC to R7C7C.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to DisplayMultiplex0/StrobeGenerator0/SLICE_0: Name Fanout Delay (ns) Site Resource ROUTE 48 1.216 OSC.OSC to R7C7C.CLK Clock -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Report Summary -------------- ---------------------------------------------------------------------------- Preference(MIN Delays) | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY NET "Clock" 14.000112 MHz ; | 0.000 ns| 0.306 ns| 1 | | | ---------------------------------------------------------------------------- All preferences were met. Clock Domains Analysis ------------------------ Found 1 clocks: Clock Domain: Clock Source: OSCH_inst.OSC Loads: 48 Covered under: FREQUENCY NET "Clock" 14.000112 MHz ; Timing summary (Hold): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 1208 paths, 1 nets, and 535 connections (94.36% coverage) Timing summary (Setup and Hold): --------------- Timing errors: 0 (setup), 0 (hold) Score: 0 (setup), 0 (hold) Cumulative negative slack: 0 (0+0) -------------------------------------------------------------------------------- --------------------------------------------------------------------------------