Lattice Synthesis Timing Report
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Lattice Synthesis Timing Report, Version  
Sun Apr 02 12:26:24 2023

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
------------------
Design:     top
Constraint file: top_temp_lse.sdc 
Report level:    verbose report, limited to 3 items per constraint
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================================================================================
Constraint: create_clock -period 71.428001 -waveform { 0.000000 35.714001 } -name Clock [ get_nets { Clock } ]
            1381 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed:  The following path meets requirements by 63.063ns

 Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)

   Source:         FD1P3AX    CK             \MatrixKeyboard0/KeyCounter_i0_i0  (from Clock +)
   Destination:    FD1P3IX    CD             \MatrixKeyboard0/KeyCounter_i0_i2  (to Clock +)

   Delay:                   8.232ns  (31.3% logic, 68.7% route), 8 logic levels.

 Constraint Details:

      8.232ns data_path \MatrixKeyboard0/KeyCounter_i0_i0 to \MatrixKeyboard0/KeyCounter_i0_i2 meets
     71.428ns delay constraint less
      0.133ns L_S requirement (totaling 71.295ns) by 63.063ns

 Path Details: \MatrixKeyboard0/KeyCounter_i0_i0 to \MatrixKeyboard0/KeyCounter_i0_i2

   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
L_CO        ---     0.367             CK to Q              \MatrixKeyboard0/KeyCounter_i0_i0 (from Clock)
Route        23   e 1.321                                  \MatrixKeyboard0/KeyCounter[0]
LUT4        ---     0.408              C to Z              \MatrixKeyboard0/i618_3_lut
Route         1   e 0.020                                  \MatrixKeyboard0/n720
MUXL5       ---     0.193           ALUT to Z              \MatrixKeyboard0/i631
Route         1   e 0.020                                  \MatrixKeyboard0/n733
MUXL5       ---     0.193             D0 to Z              \MatrixKeyboard0/i638
Route         1   e 0.660                                  \MatrixKeyboard0/n740
MUXL5       ---     0.193             D1 to Z              \MatrixKeyboard0/i641
Route         1   e 0.660                                  \MatrixKeyboard0/n743
LUT4        ---     0.408              A to Z              \MatrixKeyboard0/i643_3_lut
Route         6   e 1.018                                  \MatrixKeyboard0/KeyPressed_N_186
LUT4        ---     0.408              D to Z              \MatrixKeyboard0/i696_4_lut
Route         6   e 1.018                                  \MatrixKeyboard0/Clock_enable_43
LUT4        ---     0.408              A to Z              \MatrixKeyboard0/i687_2_lut
Route         4   e 0.937                                  \MatrixKeyboard0/n417
                  --------
                    8.232  (31.3% logic, 68.7% route), 8 logic levels.


Passed:  The following path meets requirements by 63.063ns

 Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)

   Source:         FD1P3AX    CK             \MatrixKeyboard0/KeyCounter_i0_i0  (from Clock +)
   Destination:    FD1P3IX    CD             \MatrixKeyboard0/KeyCounter_i0_i2  (to Clock +)

   Delay:                   8.232ns  (31.3% logic, 68.7% route), 8 logic levels.

 Constraint Details:

      8.232ns data_path \MatrixKeyboard0/KeyCounter_i0_i0 to \MatrixKeyboard0/KeyCounter_i0_i2 meets
     71.428ns delay constraint less
      0.133ns L_S requirement (totaling 71.295ns) by 63.063ns

 Path Details: \MatrixKeyboard0/KeyCounter_i0_i0 to \MatrixKeyboard0/KeyCounter_i0_i2

   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
L_CO        ---     0.367             CK to Q              \MatrixKeyboard0/KeyCounter_i0_i0 (from Clock)
Route        23   e 1.321                                  \MatrixKeyboard0/KeyCounter[0]
LUT4        ---     0.408              C to Z              \MatrixKeyboard0/i621_3_lut
Route         1   e 0.020                                  \MatrixKeyboard0/n723
MUXL5       ---     0.193           BLUT to Z              \MatrixKeyboard0/i633
Route         1   e 0.020                                  \MatrixKeyboard0/n735
MUXL5       ---     0.193             D0 to Z              \MatrixKeyboard0/i639
Route         1   e 0.660                                  \MatrixKeyboard0/n741
MUXL5       ---     0.193             D0 to Z              \MatrixKeyboard0/i642
Route         1   e 0.660                                  \MatrixKeyboard0/n744
LUT4        ---     0.408              B to Z              \MatrixKeyboard0/i643_3_lut
Route         6   e 1.018                                  \MatrixKeyboard0/KeyPressed_N_186
LUT4        ---     0.408              D to Z              \MatrixKeyboard0/i696_4_lut
Route         6   e 1.018                                  \MatrixKeyboard0/Clock_enable_43
LUT4        ---     0.408              A to Z              \MatrixKeyboard0/i687_2_lut
Route         4   e 0.937                                  \MatrixKeyboard0/n417
                  --------
                    8.232  (31.3% logic, 68.7% route), 8 logic levels.


Passed:  The following path meets requirements by 63.063ns

 Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)

   Source:         FD1P3AX    CK             \MatrixKeyboard0/KeyCounter_i0_i0  (from Clock +)
   Destination:    FD1P3IX    CD             \MatrixKeyboard0/KeyCounter_i0_i2  (to Clock +)

   Delay:                   8.232ns  (31.3% logic, 68.7% route), 8 logic levels.

 Constraint Details:

      8.232ns data_path \MatrixKeyboard0/KeyCounter_i0_i0 to \MatrixKeyboard0/KeyCounter_i0_i2 meets
     71.428ns delay constraint less
      0.133ns L_S requirement (totaling 71.295ns) by 63.063ns

 Path Details: \MatrixKeyboard0/KeyCounter_i0_i0 to \MatrixKeyboard0/KeyCounter_i0_i2

   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
L_CO        ---     0.367             CK to Q              \MatrixKeyboard0/KeyCounter_i0_i0 (from Clock)
Route        23   e 1.321                                  \MatrixKeyboard0/KeyCounter[0]
LUT4        ---     0.408              C to Z              \MatrixKeyboard0/i628_3_lut
Route         1   e 0.020                                  \MatrixKeyboard0/n730
MUXL5       ---     0.193           ALUT to Z              \MatrixKeyboard0/i636
Route         1   e 0.020                                  \MatrixKeyboard0/n738
MUXL5       ---     0.193             D1 to Z              \MatrixKeyboard0/i640
Route         1   e 0.660                                  \MatrixKeyboard0/n742
MUXL5       ---     0.193             D1 to Z              \MatrixKeyboard0/i642
Route         1   e 0.660                                  \MatrixKeyboard0/n744
LUT4        ---     0.408              B to Z              \MatrixKeyboard0/i643_3_lut
Route         6   e 1.018                                  \MatrixKeyboard0/KeyPressed_N_186
LUT4        ---     0.408              D to Z              \MatrixKeyboard0/i696_4_lut
Route         6   e 1.018                                  \MatrixKeyboard0/Clock_enable_43
LUT4        ---     0.408              A to Z              \MatrixKeyboard0/i687_2_lut
Route         4   e 0.937                                  \MatrixKeyboard0/n417
                  --------
                    8.232  (31.3% logic, 68.7% route), 8 logic levels.

Report: 8.365 ns is the maximum delay for this constraint.


Timing Report Summary
--------------
--------------------------------------------------------------------------------
Constraint                              |   Constraint|       Actual|Levels
--------------------------------------------------------------------------------
                                        |             |             |
create_clock -period 71.428001          |             |             |
-waveform { 0.000000 35.714001 } -name  |             |             |
Clock [ get_nets { Clock } ]            |    71.428 ns|     8.365 ns|     8  
                                        |             |             |
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All constraints were met.



Timing summary:
---------------

Timing errors: 0  Score: 0

Constraints cover  1809 paths, 170 nets, and 449 connections (66.1% coverage)


Peak memory: 59518976 bytes, TRCE: 1478656 bytes, DLYMAN: 4096 bytes
CPU_TIME_REPORT: 0 secs