Lattice Synthesis Timing Report -------------------------------------------------------------------------------- Lattice Synthesis Timing Report, Version Sun Feb 12 09:58:06 2023 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Design: top Constraint file: top_temp_lse.sdc Report level: verbose report, limited to 3 items per constraint -------------------------------------------------------------------------------- ================================================================================ Constraint: create_clock -period 5.000000 -name clk500 [get_nets \top_reveal_coretop_instance/jtck[0]] 1146 items scored, 1146 timing errors detected. -------------------------------------------------------------------------------- Error: The following path violates requirements by 11.170ns Logical Details: Cell type Pin type Cell name (clock net +/-) Source: FD1P3DX CK \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg__i26 (from \top_reveal_coretop_instance/jtck[0] +) Destination: FD1P3BX D \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_i0_i0 (to \top_reveal_coretop_instance/jtck[0] +) Delay: 16.010ns (30.3% logic, 69.7% route), 11 logic levels. Constraint Details: 16.010ns data_path \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg__i26 to \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_i0_i0 violates 5.000ns delay constraint less 0.160ns L_S requirement (totaling 4.840ns) by 11.170ns Path Details: \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg__i26 to \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_i0_i0 Name Fanout Delay (ns) Pins Resource(Cell.Net) L_CO --- 0.444 CK to Q \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg__i26 (from \top_reveal_coretop_instance/jtck[0]) Route 8 e 1.598 \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr[9] LUT4 --- 0.493 A to Z \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/i1_2_lut_rep_296 Route 8 e 1.540 \top_reveal_coretop_instance/top_la0_inst_0/n10811 LUT4 --- 0.493 C to Z \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/i1_4_lut_adj_108 Route 1 e 0.941 \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/n8932 LUT4 --- 0.493 C to Z \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/i1_3_lut_adj_148 Route 16 e 1.815 n5238 LUT4 --- 0.493 C to Z \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/i4861_3_lut Route 1 e 0.941 \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/n5526 LUT4 --- 0.493 D to Z \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/i9281_4_lut_4_lut Route 1 e 0.941 \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/n10_adj_1413 LUT4 --- 0.493 A to Z \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/n9813_bdd_3_lut Route 1 e 0.020 \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/n10688 MUXL5 --- 0.233 ALUT to Z \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/i9623 Route 1 e 0.020 \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/n10689 MUXL5 --- 0.233 D1 to Z \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/i9627 Route 3 e 1.258 \top_reveal_coretop_instance/jtdo_N_499 LUT4 --- 0.493 B to Z \top_reveal_coretop_instance/i1_2_lut Route 2 e 1.141 \top_reveal_coretop_instance/er2_tdo[0] LUT4 --- 0.493 D to Z \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/i4573_4_lut Route 1 e 0.941 \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_15__N_403[0] -------- 16.010 (30.3% logic, 69.7% route), 11 logic levels. Error: The following path violates requirements by 11.170ns Logical Details: Cell type Pin type Cell name (clock net +/-) Source: FD1P3DX CK \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg__i25 (from \top_reveal_coretop_instance/jtck[0] +) Destination: FD1P3BX D \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_i0_i0 (to \top_reveal_coretop_instance/jtck[0] +) Delay: 16.010ns (30.3% logic, 69.7% route), 11 logic levels. Constraint Details: 16.010ns data_path \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg__i25 to \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_i0_i0 violates 5.000ns delay constraint less 0.160ns L_S requirement (totaling 4.840ns) by 11.170ns Path Details: \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg__i25 to \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_i0_i0 Name Fanout Delay (ns) Pins Resource(Cell.Net) L_CO --- 0.444 CK to Q \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg__i25 (from \top_reveal_coretop_instance/jtck[0]) Route 8 e 1.598 \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr[8] LUT4 --- 0.493 B to Z \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/i1_2_lut_rep_296 Route 8 e 1.540 \top_reveal_coretop_instance/top_la0_inst_0/n10811 LUT4 --- 0.493 C to Z \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/i1_4_lut_adj_108 Route 1 e 0.941 \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/n8932 LUT4 --- 0.493 C to Z \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/i1_3_lut_adj_148 Route 16 e 1.815 n5238 LUT4 --- 0.493 C to Z \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/i4861_3_lut Route 1 e 0.941 \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/n5526 LUT4 --- 0.493 D to Z \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/i9281_4_lut_4_lut Route 1 e 0.941 \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/n10_adj_1413 LUT4 --- 0.493 A to Z \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/n9813_bdd_3_lut Route 1 e 0.020 \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/n10688 MUXL5 --- 0.233 ALUT to Z \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/i9623 Route 1 e 0.020 \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/n10689 MUXL5 --- 0.233 D1 to Z \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/i9627 Route 3 e 1.258 \top_reveal_coretop_instance/jtdo_N_499 LUT4 --- 0.493 B to Z \top_reveal_coretop_instance/i1_2_lut Route 2 e 1.141 \top_reveal_coretop_instance/er2_tdo[0] LUT4 --- 0.493 D to Z \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/i4573_4_lut Route 1 e 0.941 \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_15__N_403[0] -------- 16.010 (30.3% logic, 69.7% route), 11 logic levels. Error: The following path violates requirements by 10.687ns Logical Details: Cell type Pin type Cell name (clock net +/-) Source: FD1P3DX CK \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg__i28 (from \top_reveal_coretop_instance/jtck[0] +) Destination: FD1P3BX D \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_i0_i0 (to \top_reveal_coretop_instance/jtck[0] +) Delay: 15.527ns (31.3% logic, 68.7% route), 11 logic levels. Constraint Details: 15.527ns data_path \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg__i28 to \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_i0_i0 violates 5.000ns delay constraint less 0.160ns L_S requirement (totaling 4.840ns) by 10.687ns Path Details: \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg__i28 to \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_i0_i0 Name Fanout Delay (ns) Pins Resource(Cell.Net) L_CO --- 0.444 CK to Q \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg__i28 (from \top_reveal_coretop_instance/jtck[0]) Route 3 e 1.315 \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr[11] LUT4 --- 0.493 A to Z \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/i1_2_lut_adj_109 Route 4 e 1.340 \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/n9138 LUT4 --- 0.493 B to Z \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/i1_4_lut_adj_108 Route 1 e 0.941 \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/n8932 LUT4 --- 0.493 C to Z \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/i1_3_lut_adj_148 Route 16 e 1.815 n5238 LUT4 --- 0.493 C to Z \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/i4861_3_lut Route 1 e 0.941 \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/n5526 LUT4 --- 0.493 D to Z \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/i9281_4_lut_4_lut Route 1 e 0.941 \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/n10_adj_1413 LUT4 --- 0.493 A to Z \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/n9813_bdd_3_lut Route 1 e 0.020 \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/n10688 MUXL5 --- 0.233 ALUT to Z \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/i9623 Route 1 e 0.020 \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/n10689 MUXL5 --- 0.233 D1 to Z \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/i9627 Route 3 e 1.258 \top_reveal_coretop_instance/jtdo_N_499 LUT4 --- 0.493 B to Z \top_reveal_coretop_instance/i1_2_lut Route 2 e 1.141 \top_reveal_coretop_instance/er2_tdo[0] LUT4 --- 0.493 D to Z \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/i4573_4_lut Route 1 e 0.941 \top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc_15__N_403[0] -------- 15.527 (31.3% logic, 68.7% route), 11 logic levels. Warning: 16.170 ns is the maximum delay for this constraint. ================================================================================ Constraint: create_clock -period 71.428001 -waveform { 0.000000 35.714001 } -name Zegar [ get_nets { Clock14MHz } ] 992 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 57.902ns Logical Details: Cell type Pin type Cell name (clock net +/-) Source: FD1P3DX CK Data_i0_i24 (from Clock14MHz +) Destination: FD1S3DX D \top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d_i17 (to Clock14MHz +) Delay: 13.366ns (30.9% logic, 69.1% route), 9 logic levels. Constraint Details: 13.366ns data_path Data_i0_i24 to \top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d_i17 meets 71.428ns delay constraint less 0.160ns L_S requirement (totaling 71.268ns) by 57.902ns Path Details: Data_i0_i24 to \top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d_i17 Name Fanout Delay (ns) Pins Resource(Cell.Net) L_CO --- 0.444 CK to Q Data_i0_i24 (from Clock14MHz) Route 3 e 1.315 Data[24] LUT4 --- 0.493 A to Z \DisplayMultiplex0/i3_4_lut_adj_100 Route 2 e 1.141 \DisplayMultiplex0/Visible_6__N_183 LUT4 --- 0.493 C to Z \DisplayMultiplex0/i4_4_lut_adj_97 Route 1 e 0.941 \DisplayMultiplex0/n10_adj_1410 LUT4 --- 0.493 B to Z \DisplayMultiplex0/i5_3_lut Route 2 e 1.141 \DisplayMultiplex0/Visible[5] LUT4 --- 0.493 C to Z \DisplayMultiplex0/i4_4_lut Route 1 e 0.941 \DisplayMultiplex0/n10 LUT4 --- 0.493 B to Z \DisplayMultiplex0/i5_3_lut_rep_206 Route 1 e 0.941 \DisplayMultiplex0/n10721 LUT4 --- 0.493 B to Z \DisplayMultiplex0/n10678_bdd_3_lut_4_lut Route 12 e 1.657 reveal_ist_1_N LUT4 --- 0.493 A to Z \DisplayMultiplex0/DUT/i4559_4_lut_else_4_lut Route 1 e 0.020 \DisplayMultiplex0/DUT/n10816 MUXL5 --- 0.233 BLUT to Z \DisplayMultiplex0/DUT/i9645 Route 2 e 1.141 Segments[0]_N -------- 13.366 (30.9% logic, 69.1% route), 9 logic levels. Passed: The following path meets requirements by 57.902ns Logical Details: Cell type Pin type Cell name (clock net +/-) Source: FD1P3DX CK Data_i0_i24 (from Clock14MHz +) Destination: FD1S3DX D \top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d_i17 (to Clock14MHz +) Delay: 13.366ns (30.9% logic, 69.1% route), 9 logic levels. Constraint Details: 13.366ns data_path Data_i0_i24 to \top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d_i17 meets 71.428ns delay constraint less 0.160ns L_S requirement (totaling 71.268ns) by 57.902ns Path Details: Data_i0_i24 to \top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d_i17 Name Fanout Delay (ns) Pins Resource(Cell.Net) L_CO --- 0.444 CK to Q Data_i0_i24 (from Clock14MHz) Route 3 e 1.315 Data[24] LUT4 --- 0.493 A to Z \DisplayMultiplex0/i3_4_lut_adj_100 Route 2 e 1.141 \DisplayMultiplex0/Visible_6__N_183 LUT4 --- 0.493 C to Z \DisplayMultiplex0/i4_4_lut_adj_97 Route 1 e 0.941 \DisplayMultiplex0/n10_adj_1410 LUT4 --- 0.493 B to Z \DisplayMultiplex0/i5_3_lut Route 2 e 1.141 \DisplayMultiplex0/Visible[5] LUT4 --- 0.493 C to Z \DisplayMultiplex0/i4_4_lut Route 1 e 0.941 \DisplayMultiplex0/n10 LUT4 --- 0.493 B to Z \DisplayMultiplex0/i5_3_lut_rep_206 Route 1 e 0.941 \DisplayMultiplex0/n10721 LUT4 --- 0.493 B to Z \DisplayMultiplex0/n10678_bdd_3_lut_4_lut Route 12 e 1.657 reveal_ist_1_N LUT4 --- 0.493 A to Z \DisplayMultiplex0/DUT/i4559_4_lut_then_4_lut Route 1 e 0.020 \DisplayMultiplex0/DUT/n10817 MUXL5 --- 0.233 ALUT to Z \DisplayMultiplex0/DUT/i9645 Route 2 e 1.141 Segments[0]_N -------- 13.366 (30.9% logic, 69.1% route), 9 logic levels. Passed: The following path meets requirements by 57.902ns Logical Details: Cell type Pin type Cell name (clock net +/-) Source: FD1P3DX CK Data_i0_i24 (from Clock14MHz +) Destination: FD1S3DX D \top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d_i18 (to Clock14MHz +) Delay: 13.366ns (30.9% logic, 69.1% route), 9 logic levels. Constraint Details: 13.366ns data_path Data_i0_i24 to \top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d_i18 meets 71.428ns delay constraint less 0.160ns L_S requirement (totaling 71.268ns) by 57.902ns Path Details: Data_i0_i24 to \top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d_i18 Name Fanout Delay (ns) Pins Resource(Cell.Net) L_CO --- 0.444 CK to Q Data_i0_i24 (from Clock14MHz) Route 3 e 1.315 Data[24] LUT4 --- 0.493 A to Z \DisplayMultiplex0/i3_4_lut_adj_100 Route 2 e 1.141 \DisplayMultiplex0/Visible_6__N_183 LUT4 --- 0.493 C to Z \DisplayMultiplex0/i4_4_lut_adj_97 Route 1 e 0.941 \DisplayMultiplex0/n10_adj_1410 LUT4 --- 0.493 B to Z \DisplayMultiplex0/i5_3_lut Route 2 e 1.141 \DisplayMultiplex0/Visible[5] LUT4 --- 0.493 C to Z \DisplayMultiplex0/i4_4_lut Route 1 e 0.941 \DisplayMultiplex0/n10 LUT4 --- 0.493 B to Z \DisplayMultiplex0/i5_3_lut_rep_206 Route 1 e 0.941 \DisplayMultiplex0/n10721 LUT4 --- 0.493 B to Z \DisplayMultiplex0/n10678_bdd_3_lut_4_lut Route 12 e 1.657 reveal_ist_1_N LUT4 --- 0.493 A to Z \DisplayMultiplex0/DUT/i4524_4_lut_then_4_lut Route 1 e 0.020 \DisplayMultiplex0/DUT/n10820 MUXL5 --- 0.233 ALUT to Z \DisplayMultiplex0/DUT/i9647 Route 2 e 1.141 Segments[1]_N -------- 13.366 (30.9% logic, 69.1% route), 9 logic levels. Report: 13.526 ns is the maximum delay for this constraint. Timing Report Summary -------------- -------------------------------------------------------------------------------- Constraint | Constraint| Actual|Levels -------------------------------------------------------------------------------- | | | create_clock -period 5.000000 -name | | | clk500 [get_nets | | | \top_reveal_coretop_instance/jtck[0]] | 5.000 ns| 16.170 ns| 11 * | | | create_clock -period 71.428001 | | | -waveform { 0.000000 35.714001 } -name | | | Zegar [ get_nets { Clock14MHz } ] | 71.428 ns| 13.526 ns| 9 | | | -------------------------------------------------------------------------------- 1 constraints not met. -------------------------------------------------------------------------------- Critical Nets | Loads| Errors| % of total -------------------------------------------------------------------------------- \top_reveal_coretop_instance/top_la0_ins| | | t_0/n108 | 8| 621| 54.19% | | | \top_reveal_coretop_instance/top_la0_ins| | | t_0/n8105 | 2| 377| 32.90% | | | \top_reveal_coretop_instance/top_la0_ins| | | t_0/tm_u/n7591 | 1| 255| 22.25% | | | \top_reveal_coretop_instance/top_la0_ins| | | t_0/tm_u/n7592 | 1| 251| 21.90% | | | \top_reveal_coretop_instance/top_la0_ins| | | t_0/n97 | 3| 247| 21.55% | | | \top_reveal_coretop_instance/top_la0_ins| | | t_0/jtag_int_u/n6_adj_1414 | 4| 147| 12.83% | | | \top_reveal_coretop_instance/top_la0_ins| | | t_0/jtag_int_u/n10773 | 5| 146| 12.74% | | | \top_reveal_coretop_instance/top_la0_ins| | | t_0/tm_u/n16 | 1| 143| 12.48% | | | \top_reveal_coretop_instance/top_la0_ins| | | t_0/jtag_int_u/n10781 | 3| 134| 11.69% | | | \top_reveal_coretop_instance/top_la0_ins| | | t_0/tm_u/n38 | 1| 132| 11.52% | | | \top_reveal_coretop_instance/top_la0_ins| | | t_0/tm_u/n7590 | 1| 129| 11.26% | | | \top_reveal_coretop_instance/top_la0_ins| | | t_0/trig_u/te_0/n2774 | 18| 122| 10.65% | | | \top_reveal_coretop_instance/top_la0_ins| | | t_0/n10772 | 3| 120| 10.47% | | | \top_reveal_coretop_instance/top_la0_ins| | | t_0/cmd_block | 2| 117| 10.21% | | | \top_reveal_coretop_instance/top_la0_ins| | | t_0/tm_u/n7593 | 1| 117| 10.21% | | | \top_reveal_coretop_instance/jtdo_N_499 | 3| 116| 10.12% | | | -------------------------------------------------------------------------------- Timing summary: --------------- Timing errors: 1146 Score: 5459888 Constraints cover 10507 paths, 1455 nets, and 3821 connections (79.8% coverage) Peak memory: 77529088 bytes, TRCE: 3039232 bytes, DLYMAN: 327680 bytes CPU_TIME_REPORT: 0 secs