--------------------------------------------------------------------------------
Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
Sun Feb 05 12:37:50 2023

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
------------------
Design file:     top
Device,speed:    LCMXO2-1200HC,4
Report level:    verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------



================================================================================
Preference: FREQUENCY NET "Clock14MHz" 14.000112 MHz ;
            10 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
 

Passed: The following path meets requirements by 62.058ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              DecimalStrobeGenerator/Counter_i7  (from Clock14MHz +)
   Destination:    FF         Data in        DecimalStrobeGenerator/Counter_i23  (to Clock14MHz +)

   Delay:               9.096ns  (21.3% logic, 78.7% route), 4 logic levels.

 Constraint Details:

      9.096ns physical path delay DecimalStrobeGenerator/SLICE_35 to DecimalStrobeGenerator/SLICE_46 meets
     71.428ns delay constraint less
      0.000ns skew and
      0.274ns LSR_SET requirement (totaling 71.154ns) by 62.058ns

 Physical Path Details:

      Data path DecimalStrobeGenerator/SLICE_35 to DecimalStrobeGenerator/SLICE_46:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.452     R7C10A.CLK to      R7C10A.Q0 DecimalStrobeGenerator/SLICE_35 (from Clock14MHz)
ROUTE         2     1.854      R7C10A.Q0 to R9C12A.B1      DecimalStrobeGenerator/Counter_7
CTOF_DEL    ---     0.495      R9C12A.B1 to      R9C12A.F1 SLICE_50
ROUTE         1     1.336      R9C12A.F1 to R8C10A.B0      DecimalStrobeGenerator/n40
CTOF_DEL    ---     0.495      R8C10A.B0 to      R8C10A.F0 DecimalStrobeGenerator/SLICE_78
ROUTE         1     1.079      R8C10A.F0 to R7C12D.C0      DecimalStrobeGenerator/n44
CTOF_DEL    ---     0.495      R7C12D.C0 to      R7C12D.F0 DecimalStrobeGenerator/SLICE_48
ROUTE        14     2.890      R7C12D.F0 to R7C12A.LSR     DecimalStrobeGenerator/Counter_23__N_170 (to Clock14MHz)
                  --------
                    9.096   (21.3% logic, 78.7% route), 4 logic levels.

 Clock Skew Details: 

      Source Clock Path OSCH_inst to DecimalStrobeGenerator/SLICE_35:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        56     3.541        OSC.OSC to R7C10A.CLK     Clock14MHz
                  --------
                    3.541   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path OSCH_inst to DecimalStrobeGenerator/SLICE_46:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        56     3.541        OSC.OSC to R7C12A.CLK     Clock14MHz
                  --------
                    3.541   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 62.058ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              DecimalStrobeGenerator/Counter_i7  (from Clock14MHz +)
   Destination:    FF         Data in        DecimalStrobeGenerator/Counter_i20  (to Clock14MHz +)
                   FF                        DecimalStrobeGenerator/Counter_i19

   Delay:               9.096ns  (21.3% logic, 78.7% route), 4 logic levels.

 Constraint Details:

      9.096ns physical path delay DecimalStrobeGenerator/SLICE_35 to DecimalStrobeGenerator/SLICE_41 meets
     71.428ns delay constraint less
      0.000ns skew and
      0.274ns LSR_SET requirement (totaling 71.154ns) by 62.058ns

 Physical Path Details:

      Data path DecimalStrobeGenerator/SLICE_35 to DecimalStrobeGenerator/SLICE_41:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.452     R7C10A.CLK to      R7C10A.Q0 DecimalStrobeGenerator/SLICE_35 (from Clock14MHz)
ROUTE         2     1.854      R7C10A.Q0 to R9C12A.B1      DecimalStrobeGenerator/Counter_7
CTOF_DEL    ---     0.495      R9C12A.B1 to      R9C12A.F1 SLICE_50
ROUTE         1     1.336      R9C12A.F1 to R8C10A.B0      DecimalStrobeGenerator/n40
CTOF_DEL    ---     0.495      R8C10A.B0 to      R8C10A.F0 DecimalStrobeGenerator/SLICE_78
ROUTE         1     1.079      R8C10A.F0 to R7C12D.C0      DecimalStrobeGenerator/n44
CTOF_DEL    ---     0.495      R7C12D.C0 to      R7C12D.F0 DecimalStrobeGenerator/SLICE_48
ROUTE        14     2.890      R7C12D.F0 to R7C11C.LSR     DecimalStrobeGenerator/Counter_23__N_170 (to Clock14MHz)
                  --------
                    9.096   (21.3% logic, 78.7% route), 4 logic levels.

 Clock Skew Details: 

      Source Clock Path OSCH_inst to DecimalStrobeGenerator/SLICE_35:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        56     3.541        OSC.OSC to R7C10A.CLK     Clock14MHz
                  --------
                    3.541   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path OSCH_inst to DecimalStrobeGenerator/SLICE_41:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        56     3.541        OSC.OSC to R7C11C.CLK     Clock14MHz
                  --------
                    3.541   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 62.058ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              DecimalStrobeGenerator/Counter_i7  (from Clock14MHz +)
   Destination:    FF         Data in        DecimalStrobeGenerator/Counter_i2  (to Clock14MHz +)
                   FF                        DecimalStrobeGenerator/Counter_i1

   Delay:               9.096ns  (21.3% logic, 78.7% route), 4 logic levels.

 Constraint Details:

      9.096ns physical path delay DecimalStrobeGenerator/SLICE_35 to DecimalStrobeGenerator/SLICE_39 meets
     71.428ns delay constraint less
      0.000ns skew and
      0.274ns LSR_SET requirement (totaling 71.154ns) by 62.058ns

 Physical Path Details:

      Data path DecimalStrobeGenerator/SLICE_35 to DecimalStrobeGenerator/SLICE_39:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.452     R7C10A.CLK to      R7C10A.Q0 DecimalStrobeGenerator/SLICE_35 (from Clock14MHz)
ROUTE         2     1.854      R7C10A.Q0 to R9C12A.B1      DecimalStrobeGenerator/Counter_7
CTOF_DEL    ---     0.495      R9C12A.B1 to      R9C12A.F1 SLICE_50
ROUTE         1     1.336      R9C12A.F1 to R8C10A.B0      DecimalStrobeGenerator/n40
CTOF_DEL    ---     0.495      R8C10A.B0 to      R8C10A.F0 DecimalStrobeGenerator/SLICE_78
ROUTE         1     1.079      R8C10A.F0 to R7C12D.C0      DecimalStrobeGenerator/n44
CTOF_DEL    ---     0.495      R7C12D.C0 to      R7C12D.F0 DecimalStrobeGenerator/SLICE_48
ROUTE        14     2.890      R7C12D.F0 to R7C9B.LSR      DecimalStrobeGenerator/Counter_23__N_170 (to Clock14MHz)
                  --------
                    9.096   (21.3% logic, 78.7% route), 4 logic levels.

 Clock Skew Details: 

      Source Clock Path OSCH_inst to DecimalStrobeGenerator/SLICE_35:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        56     3.541        OSC.OSC to R7C10A.CLK     Clock14MHz
                  --------
                    3.541   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path OSCH_inst to DecimalStrobeGenerator/SLICE_39:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        56     3.541        OSC.OSC to R7C9B.CLK      Clock14MHz
                  --------
                    3.541   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 62.058ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              DecimalStrobeGenerator/Counter_i7  (from Clock14MHz +)
   Destination:    FF         Data in        DecimalStrobeGenerator/Counter_i4  (to Clock14MHz +)
                   FF                        DecimalStrobeGenerator/Counter_i3

   Delay:               9.096ns  (21.3% logic, 78.7% route), 4 logic levels.

 Constraint Details:

      9.096ns physical path delay DecimalStrobeGenerator/SLICE_35 to DecimalStrobeGenerator/SLICE_37 meets
     71.428ns delay constraint less
      0.000ns skew and
      0.274ns LSR_SET requirement (totaling 71.154ns) by 62.058ns

 Physical Path Details:

      Data path DecimalStrobeGenerator/SLICE_35 to DecimalStrobeGenerator/SLICE_37:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.452     R7C10A.CLK to      R7C10A.Q0 DecimalStrobeGenerator/SLICE_35 (from Clock14MHz)
ROUTE         2     1.854      R7C10A.Q0 to R9C12A.B1      DecimalStrobeGenerator/Counter_7
CTOF_DEL    ---     0.495      R9C12A.B1 to      R9C12A.F1 SLICE_50
ROUTE         1     1.336      R9C12A.F1 to R8C10A.B0      DecimalStrobeGenerator/n40
CTOF_DEL    ---     0.495      R8C10A.B0 to      R8C10A.F0 DecimalStrobeGenerator/SLICE_78
ROUTE         1     1.079      R8C10A.F0 to R7C12D.C0      DecimalStrobeGenerator/n44
CTOF_DEL    ---     0.495      R7C12D.C0 to      R7C12D.F0 DecimalStrobeGenerator/SLICE_48
ROUTE        14     2.890      R7C12D.F0 to R7C9C.LSR      DecimalStrobeGenerator/Counter_23__N_170 (to Clock14MHz)
                  --------
                    9.096   (21.3% logic, 78.7% route), 4 logic levels.

 Clock Skew Details: 

      Source Clock Path OSCH_inst to DecimalStrobeGenerator/SLICE_35:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        56     3.541        OSC.OSC to R7C10A.CLK     Clock14MHz
                  --------
                    3.541   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path OSCH_inst to DecimalStrobeGenerator/SLICE_37:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        56     3.541        OSC.OSC to R7C9C.CLK      Clock14MHz
                  --------
                    3.541   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 62.058ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              DecimalStrobeGenerator/Counter_i7  (from Clock14MHz +)
   Destination:    FF         Data in        DecimalStrobeGenerator/Counter_i8  (to Clock14MHz +)
                   FF                        DecimalStrobeGenerator/Counter_i7

   Delay:               9.096ns  (21.3% logic, 78.7% route), 4 logic levels.

 Constraint Details:

      9.096ns physical path delay DecimalStrobeGenerator/SLICE_35 to DecimalStrobeGenerator/SLICE_35 meets
     71.428ns delay constraint less
      0.000ns skew and
      0.274ns LSR_SET requirement (totaling 71.154ns) by 62.058ns

 Physical Path Details:

      Data path DecimalStrobeGenerator/SLICE_35 to DecimalStrobeGenerator/SLICE_35:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.452     R7C10A.CLK to      R7C10A.Q0 DecimalStrobeGenerator/SLICE_35 (from Clock14MHz)
ROUTE         2     1.854      R7C10A.Q0 to R9C12A.B1      DecimalStrobeGenerator/Counter_7
CTOF_DEL    ---     0.495      R9C12A.B1 to      R9C12A.F1 SLICE_50
ROUTE         1     1.336      R9C12A.F1 to R8C10A.B0      DecimalStrobeGenerator/n40
CTOF_DEL    ---     0.495      R8C10A.B0 to      R8C10A.F0 DecimalStrobeGenerator/SLICE_78
ROUTE         1     1.079      R8C10A.F0 to R7C12D.C0      DecimalStrobeGenerator/n44
CTOF_DEL    ---     0.495      R7C12D.C0 to      R7C12D.F0 DecimalStrobeGenerator/SLICE_48
ROUTE        14     2.890      R7C12D.F0 to R7C10A.LSR     DecimalStrobeGenerator/Counter_23__N_170 (to Clock14MHz)
                  --------
                    9.096   (21.3% logic, 78.7% route), 4 logic levels.

 Clock Skew Details: 

      Source Clock Path OSCH_inst to DecimalStrobeGenerator/SLICE_35:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        56     3.541        OSC.OSC to R7C10A.CLK     Clock14MHz
                  --------
                    3.541   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path OSCH_inst to DecimalStrobeGenerator/SLICE_35:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        56     3.541        OSC.OSC to R7C10A.CLK     Clock14MHz
                  --------
                    3.541   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 62.058ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              DecimalStrobeGenerator/Counter_i7  (from Clock14MHz +)
   Destination:    FF         Data in        DecimalStrobeGenerator/Counter_i0  (to Clock14MHz +)

   Delay:               9.096ns  (21.3% logic, 78.7% route), 4 logic levels.

 Constraint Details:

      9.096ns physical path delay DecimalStrobeGenerator/SLICE_35 to DecimalStrobeGenerator/SLICE_40 meets
     71.428ns delay constraint less
      0.000ns skew and
      0.274ns LSR_SET requirement (totaling 71.154ns) by 62.058ns

 Physical Path Details:

      Data path DecimalStrobeGenerator/SLICE_35 to DecimalStrobeGenerator/SLICE_40:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.452     R7C10A.CLK to      R7C10A.Q0 DecimalStrobeGenerator/SLICE_35 (from Clock14MHz)
ROUTE         2     1.854      R7C10A.Q0 to R9C12A.B1      DecimalStrobeGenerator/Counter_7
CTOF_DEL    ---     0.495      R9C12A.B1 to      R9C12A.F1 SLICE_50
ROUTE         1     1.336      R9C12A.F1 to R8C10A.B0      DecimalStrobeGenerator/n40
CTOF_DEL    ---     0.495      R8C10A.B0 to      R8C10A.F0 DecimalStrobeGenerator/SLICE_78
ROUTE         1     1.079      R8C10A.F0 to R7C12D.C0      DecimalStrobeGenerator/n44
CTOF_DEL    ---     0.495      R7C12D.C0 to      R7C12D.F0 DecimalStrobeGenerator/SLICE_48
ROUTE        14     2.890      R7C12D.F0 to R7C9A.LSR      DecimalStrobeGenerator/Counter_23__N_170 (to Clock14MHz)
                  --------
                    9.096   (21.3% logic, 78.7% route), 4 logic levels.

 Clock Skew Details: 

      Source Clock Path OSCH_inst to DecimalStrobeGenerator/SLICE_35:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        56     3.541        OSC.OSC to R7C10A.CLK     Clock14MHz
                  --------
                    3.541   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path OSCH_inst to DecimalStrobeGenerator/SLICE_40:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        56     3.541        OSC.OSC to R7C9A.CLK      Clock14MHz
                  --------
                    3.541   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 62.058ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              DecimalStrobeGenerator/Counter_i7  (from Clock14MHz +)
   Destination:    FF         Data in        DecimalStrobeGenerator/Counter_i18  (to Clock14MHz +)
                   FF                        DecimalStrobeGenerator/Counter_i17

   Delay:               9.096ns  (21.3% logic, 78.7% route), 4 logic levels.

 Constraint Details:

      9.096ns physical path delay DecimalStrobeGenerator/SLICE_35 to DecimalStrobeGenerator/SLICE_42 meets
     71.428ns delay constraint less
      0.000ns skew and
      0.274ns LSR_SET requirement (totaling 71.154ns) by 62.058ns

 Physical Path Details:

      Data path DecimalStrobeGenerator/SLICE_35 to DecimalStrobeGenerator/SLICE_42:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.452     R7C10A.CLK to      R7C10A.Q0 DecimalStrobeGenerator/SLICE_35 (from Clock14MHz)
ROUTE         2     1.854      R7C10A.Q0 to R9C12A.B1      DecimalStrobeGenerator/Counter_7
CTOF_DEL    ---     0.495      R9C12A.B1 to      R9C12A.F1 SLICE_50
ROUTE         1     1.336      R9C12A.F1 to R8C10A.B0      DecimalStrobeGenerator/n40
CTOF_DEL    ---     0.495      R8C10A.B0 to      R8C10A.F0 DecimalStrobeGenerator/SLICE_78
ROUTE         1     1.079      R8C10A.F0 to R7C12D.C0      DecimalStrobeGenerator/n44
CTOF_DEL    ---     0.495      R7C12D.C0 to      R7C12D.F0 DecimalStrobeGenerator/SLICE_48
ROUTE        14     2.890      R7C12D.F0 to R7C11B.LSR     DecimalStrobeGenerator/Counter_23__N_170 (to Clock14MHz)
                  --------
                    9.096   (21.3% logic, 78.7% route), 4 logic levels.

 Clock Skew Details: 

      Source Clock Path OSCH_inst to DecimalStrobeGenerator/SLICE_35:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        56     3.541        OSC.OSC to R7C10A.CLK     Clock14MHz
                  --------
                    3.541   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path OSCH_inst to DecimalStrobeGenerator/SLICE_42:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        56     3.541        OSC.OSC to R7C11B.CLK     Clock14MHz
                  --------
                    3.541   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 62.058ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              DecimalStrobeGenerator/Counter_i7  (from Clock14MHz +)
   Destination:    FF         Data in        DecimalStrobeGenerator/Counter_i6  (to Clock14MHz +)
                   FF                        DecimalStrobeGenerator/Counter_i5

   Delay:               9.096ns  (21.3% logic, 78.7% route), 4 logic levels.

 Constraint Details:

      9.096ns physical path delay DecimalStrobeGenerator/SLICE_35 to DecimalStrobeGenerator/SLICE_36 meets
     71.428ns delay constraint less
      0.000ns skew and
      0.274ns LSR_SET requirement (totaling 71.154ns) by 62.058ns

 Physical Path Details:

      Data path DecimalStrobeGenerator/SLICE_35 to DecimalStrobeGenerator/SLICE_36:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.452     R7C10A.CLK to      R7C10A.Q0 DecimalStrobeGenerator/SLICE_35 (from Clock14MHz)
ROUTE         2     1.854      R7C10A.Q0 to R9C12A.B1      DecimalStrobeGenerator/Counter_7
CTOF_DEL    ---     0.495      R9C12A.B1 to      R9C12A.F1 SLICE_50
ROUTE         1     1.336      R9C12A.F1 to R8C10A.B0      DecimalStrobeGenerator/n40
CTOF_DEL    ---     0.495      R8C10A.B0 to      R8C10A.F0 DecimalStrobeGenerator/SLICE_78
ROUTE         1     1.079      R8C10A.F0 to R7C12D.C0      DecimalStrobeGenerator/n44
CTOF_DEL    ---     0.495      R7C12D.C0 to      R7C12D.F0 DecimalStrobeGenerator/SLICE_48
ROUTE        14     2.890      R7C12D.F0 to R7C9D.LSR      DecimalStrobeGenerator/Counter_23__N_170 (to Clock14MHz)
                  --------
                    9.096   (21.3% logic, 78.7% route), 4 logic levels.

 Clock Skew Details: 

      Source Clock Path OSCH_inst to DecimalStrobeGenerator/SLICE_35:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        56     3.541        OSC.OSC to R7C10A.CLK     Clock14MHz
                  --------
                    3.541   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path OSCH_inst to DecimalStrobeGenerator/SLICE_36:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        56     3.541        OSC.OSC to R7C9D.CLK      Clock14MHz
                  --------
                    3.541   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 62.058ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              DecimalStrobeGenerator/Counter_i7  (from Clock14MHz +)
   Destination:    FF         Data in        DecimalStrobeGenerator/Counter_i22  (to Clock14MHz +)
                   FF                        DecimalStrobeGenerator/Counter_i21

   Delay:               9.096ns  (21.3% logic, 78.7% route), 4 logic levels.

 Constraint Details:

      9.096ns physical path delay DecimalStrobeGenerator/SLICE_35 to DecimalStrobeGenerator/SLICE_38 meets
     71.428ns delay constraint less
      0.000ns skew and
      0.274ns LSR_SET requirement (totaling 71.154ns) by 62.058ns

 Physical Path Details:

      Data path DecimalStrobeGenerator/SLICE_35 to DecimalStrobeGenerator/SLICE_38:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.452     R7C10A.CLK to      R7C10A.Q0 DecimalStrobeGenerator/SLICE_35 (from Clock14MHz)
ROUTE         2     1.854      R7C10A.Q0 to R9C12A.B1      DecimalStrobeGenerator/Counter_7
CTOF_DEL    ---     0.495      R9C12A.B1 to      R9C12A.F1 SLICE_50
ROUTE         1     1.336      R9C12A.F1 to R8C10A.B0      DecimalStrobeGenerator/n40
CTOF_DEL    ---     0.495      R8C10A.B0 to      R8C10A.F0 DecimalStrobeGenerator/SLICE_78
ROUTE         1     1.079      R8C10A.F0 to R7C12D.C0      DecimalStrobeGenerator/n44
CTOF_DEL    ---     0.495      R7C12D.C0 to      R7C12D.F0 DecimalStrobeGenerator/SLICE_48
ROUTE        14     2.890      R7C12D.F0 to R7C11D.LSR     DecimalStrobeGenerator/Counter_23__N_170 (to Clock14MHz)
                  --------
                    9.096   (21.3% logic, 78.7% route), 4 logic levels.

 Clock Skew Details: 

      Source Clock Path OSCH_inst to DecimalStrobeGenerator/SLICE_35:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        56     3.541        OSC.OSC to R7C10A.CLK     Clock14MHz
                  --------
                    3.541   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path OSCH_inst to DecimalStrobeGenerator/SLICE_38:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        56     3.541        OSC.OSC to R7C11D.CLK     Clock14MHz
                  --------
                    3.541   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 62.058ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              DecimalStrobeGenerator/Counter_i7  (from Clock14MHz +)
   Destination:    FF         Data in        DecimalStrobeGenerator/Counter_i10  (to Clock14MHz +)
                   FF                        DecimalStrobeGenerator/Counter_i9

   Delay:               9.096ns  (21.3% logic, 78.7% route), 4 logic levels.

 Constraint Details:

      9.096ns physical path delay DecimalStrobeGenerator/SLICE_35 to DecimalStrobeGenerator/SLICE_34 meets
     71.428ns delay constraint less
      0.000ns skew and
      0.274ns LSR_SET requirement (totaling 71.154ns) by 62.058ns

 Physical Path Details:

      Data path DecimalStrobeGenerator/SLICE_35 to DecimalStrobeGenerator/SLICE_34:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.452     R7C10A.CLK to      R7C10A.Q0 DecimalStrobeGenerator/SLICE_35 (from Clock14MHz)
ROUTE         2     1.854      R7C10A.Q0 to R9C12A.B1      DecimalStrobeGenerator/Counter_7
CTOF_DEL    ---     0.495      R9C12A.B1 to      R9C12A.F1 SLICE_50
ROUTE         1     1.336      R9C12A.F1 to R8C10A.B0      DecimalStrobeGenerator/n40
CTOF_DEL    ---     0.495      R8C10A.B0 to      R8C10A.F0 DecimalStrobeGenerator/SLICE_78
ROUTE         1     1.079      R8C10A.F0 to R7C12D.C0      DecimalStrobeGenerator/n44
CTOF_DEL    ---     0.495      R7C12D.C0 to      R7C12D.F0 DecimalStrobeGenerator/SLICE_48
ROUTE        14     2.890      R7C12D.F0 to R7C10B.LSR     DecimalStrobeGenerator/Counter_23__N_170 (to Clock14MHz)
                  --------
                    9.096   (21.3% logic, 78.7% route), 4 logic levels.

 Clock Skew Details: 

      Source Clock Path OSCH_inst to DecimalStrobeGenerator/SLICE_35:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        56     3.541        OSC.OSC to R7C10A.CLK     Clock14MHz
                  --------
                    3.541   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path OSCH_inst to DecimalStrobeGenerator/SLICE_34:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        56     3.541        OSC.OSC to R7C10B.CLK     Clock14MHz
                  --------
                    3.541   (0.0% logic, 100.0% route), 0 logic levels.

Report:  106.724MHz is the maximum frequency for this preference.

Report Summary
--------------
----------------------------------------------------------------------------
Preference                              |   Constraint|       Actual|Levels
----------------------------------------------------------------------------
                                        |             |             |
FREQUENCY NET "Clock14MHz" 14.000112    |             |             |
MHz ;                                   |   14.000 MHz|  106.724 MHz|   4  
                                        |             |             |
----------------------------------------------------------------------------


All preferences were met.


Clock Domains Analysis
------------------------

Found 1 clocks:

Clock Domain: Clock14MHz   Source: OSCH_inst.OSC   Loads: 56
   Covered under: FREQUENCY NET "Clock14MHz" 14.000112 MHz ;


Timing summary (Setup):
---------------

Timing errors: 0  Score: 0
Cumulative negative slack: 0

Constraints cover 1827 paths, 1 nets, and 641 connections (100.00% coverage)