-------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 Sun Feb 05 12:37:50 2023 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Design file: top Device,speed: LCMXO2-1200HC,M Report level: verbose report, limited to 10 items per preference -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY NET "Clock14MHz" 14.000112 MHz ; 10 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 0.303ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DecimalStrobeGenerator/Strobe_13 (from Clock14MHz +) Destination: FF Data in DecimalPoints_i0_i1 (to Clock14MHz +) FF DecimalPoints_i0_i0 Delay: 0.279ns (47.7% logic, 52.3% route), 1 logic levels. Constraint Details: 0.279ns physical path delay DecimalStrobeGenerator/SLICE_48 to SLICE_83 meets -0.024ns CE_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.024ns) by 0.303ns Physical Path Details: Data path DecimalStrobeGenerator/SLICE_48 to SLICE_83: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R7C12D.CLK to R7C12D.Q0 DecimalStrobeGenerator/SLICE_48 (from Clock14MHz) ROUTE 4 0.146 R7C12D.Q0 to R7C12C.CE DecimalPointMoveEnable (to Clock14MHz) -------- 0.279 (47.7% logic, 52.3% route), 1 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to DecimalStrobeGenerator/SLICE_48: Name Fanout Delay (ns) Site Resource ROUTE 56 1.216 OSC.OSC to R7C12D.CLK Clock14MHz -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_83: Name Fanout Delay (ns) Site Resource ROUTE 56 1.216 OSC.OSC to R7C12C.CLK Clock14MHz -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.306ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DecimalPoints_i0_i2 (from Clock14MHz +) Destination: FF Data in DecimalPoints_i0_i3 (to Clock14MHz +) Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. Constraint Details: 0.287ns physical path delay SLICE_50 to SLICE_50 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.306ns Physical Path Details: Data path SLICE_50 to SLICE_50: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R9C12A.CLK to R9C12A.Q0 SLICE_50 (from Clock14MHz) ROUTE 2 0.154 R9C12A.Q0 to R9C12A.M1 DecimalPoints_2 (to Clock14MHz) -------- 0.287 (46.3% logic, 53.7% route), 1 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_50: Name Fanout Delay (ns) Site Resource ROUTE 56 1.216 OSC.OSC to R9C12A.CLK Clock14MHz -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_50: Name Fanout Delay (ns) Site Resource ROUTE 56 1.216 OSC.OSC to R9C12A.CLK Clock14MHz -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.306ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DecimalPoints_i0_i4 (from Clock14MHz +) Destination: FF Data in DecimalPoints_i0_i5 (to Clock14MHz +) Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. Constraint Details: 0.287ns physical path delay SLICE_51 to SLICE_51 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.306ns Physical Path Details: Data path SLICE_51 to SLICE_51: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R9C14C.CLK to R9C14C.Q0 SLICE_51 (from Clock14MHz) ROUTE 2 0.154 R9C14C.Q0 to R9C14C.M1 DecimalPoints_4 (to Clock14MHz) -------- 0.287 (46.3% logic, 53.7% route), 1 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_51: Name Fanout Delay (ns) Site Resource ROUTE 56 1.216 OSC.OSC to R9C14C.CLK Clock14MHz -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_51: Name Fanout Delay (ns) Site Resource ROUTE 56 1.216 OSC.OSC to R9C14C.CLK Clock14MHz -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.306ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DecimalPoints_i0_i6 (from Clock14MHz +) Destination: FF Data in DecimalPoints_i0_i7 (to Clock14MHz +) Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. Constraint Details: 0.287ns physical path delay SLICE_52 to SLICE_52 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.306ns Physical Path Details: Data path SLICE_52 to SLICE_52: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R7C14A.CLK to R7C14A.Q0 SLICE_52 (from Clock14MHz) ROUTE 2 0.154 R7C14A.Q0 to R7C14A.M1 DecimalPoints_6 (to Clock14MHz) -------- 0.287 (46.3% logic, 53.7% route), 1 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_52: Name Fanout Delay (ns) Site Resource ROUTE 56 1.216 OSC.OSC to R7C14A.CLK Clock14MHz -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_52: Name Fanout Delay (ns) Site Resource ROUTE 56 1.216 OSC.OSC to R7C14A.CLK Clock14MHz -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.306ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DecimalPoints_i0_i0 (from Clock14MHz +) Destination: FF Data in DecimalPoints_i0_i1 (to Clock14MHz +) Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. Constraint Details: 0.287ns physical path delay SLICE_83 to SLICE_83 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.306ns Physical Path Details: Data path SLICE_83 to SLICE_83: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R7C12C.CLK to R7C12C.Q0 SLICE_83 (from Clock14MHz) ROUTE 2 0.154 R7C12C.Q0 to R7C12C.M1 DecimalPoints_0 (to Clock14MHz) -------- 0.287 (46.3% logic, 53.7% route), 1 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_83: Name Fanout Delay (ns) Site Resource ROUTE 56 1.216 OSC.OSC to R7C12C.CLK Clock14MHz -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_83: Name Fanout Delay (ns) Site Resource ROUTE 56 1.216 OSC.OSC to R7C12C.CLK Clock14MHz -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q CountStrobeGenerator/Counter_i12 (from Clock14MHz +) Destination: FF Data in CountStrobeGenerator/Counter_i12 (to Clock14MHz +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay CountStrobeGenerator/SLICE_21 to CountStrobeGenerator/SLICE_21 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path CountStrobeGenerator/SLICE_21 to CountStrobeGenerator/SLICE_21: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R5C14C.CLK to R5C14C.Q1 CountStrobeGenerator/SLICE_21 (from Clock14MHz) ROUTE 2 0.132 R5C14C.Q1 to R5C14C.A1 CountStrobeGenerator/Counter_12 CTOF_DEL --- 0.101 R5C14C.A1 to R5C14C.F1 CountStrobeGenerator/SLICE_21 ROUTE 1 0.000 R5C14C.F1 to R5C14C.DI1 CountStrobeGenerator/Counter_20_N_98_12 (to Clock14MHz) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to CountStrobeGenerator/SLICE_21: Name Fanout Delay (ns) Site Resource ROUTE 56 1.216 OSC.OSC to R5C14C.CLK Clock14MHz -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to CountStrobeGenerator/SLICE_21: Name Fanout Delay (ns) Site Resource ROUTE 56 1.216 OSC.OSC to R5C14C.CLK Clock14MHz -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DecimalStrobeGenerator/Counter_i2 (from Clock14MHz +) Destination: FF Data in DecimalStrobeGenerator/Counter_i2 (to Clock14MHz +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay DecimalStrobeGenerator/SLICE_39 to DecimalStrobeGenerator/SLICE_39 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path DecimalStrobeGenerator/SLICE_39 to DecimalStrobeGenerator/SLICE_39: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R7C9B.CLK to R7C9B.Q1 DecimalStrobeGenerator/SLICE_39 (from Clock14MHz) ROUTE 2 0.132 R7C9B.Q1 to R7C9B.A1 DecimalStrobeGenerator/Counter_2 CTOF_DEL --- 0.101 R7C9B.A1 to R7C9B.F1 DecimalStrobeGenerator/SLICE_39 ROUTE 1 0.000 R7C9B.F1 to R7C9B.DI1 DecimalStrobeGenerator/Counter_23_N_146_2 (to Clock14MHz) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to DecimalStrobeGenerator/SLICE_39: Name Fanout Delay (ns) Site Resource ROUTE 56 1.216 OSC.OSC to R7C9B.CLK Clock14MHz -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to DecimalStrobeGenerator/SLICE_39: Name Fanout Delay (ns) Site Resource ROUTE 56 1.216 OSC.OSC to R7C9B.CLK Clock14MHz -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DecimalStrobeGenerator/Counter_i7 (from Clock14MHz +) Destination: FF Data in DecimalStrobeGenerator/Counter_i7 (to Clock14MHz +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay DecimalStrobeGenerator/SLICE_35 to DecimalStrobeGenerator/SLICE_35 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path DecimalStrobeGenerator/SLICE_35 to DecimalStrobeGenerator/SLICE_35: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R7C10A.CLK to R7C10A.Q0 DecimalStrobeGenerator/SLICE_35 (from Clock14MHz) ROUTE 2 0.132 R7C10A.Q0 to R7C10A.A0 DecimalStrobeGenerator/Counter_7 CTOF_DEL --- 0.101 R7C10A.A0 to R7C10A.F0 DecimalStrobeGenerator/SLICE_35 ROUTE 1 0.000 R7C10A.F0 to R7C10A.DI0 DecimalStrobeGenerator/Counter_23_N_146_7 (to Clock14MHz) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to DecimalStrobeGenerator/SLICE_35: Name Fanout Delay (ns) Site Resource ROUTE 56 1.216 OSC.OSC to R7C10A.CLK Clock14MHz -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to DecimalStrobeGenerator/SLICE_35: Name Fanout Delay (ns) Site Resource ROUTE 56 1.216 OSC.OSC to R7C10A.CLK Clock14MHz -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DecimalStrobeGenerator/Counter_i0 (from Clock14MHz +) Destination: FF Data in DecimalStrobeGenerator/Counter_i0 (to Clock14MHz +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay DecimalStrobeGenerator/SLICE_40 to DecimalStrobeGenerator/SLICE_40 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path DecimalStrobeGenerator/SLICE_40 to DecimalStrobeGenerator/SLICE_40: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R7C9A.CLK to R7C9A.Q1 DecimalStrobeGenerator/SLICE_40 (from Clock14MHz) ROUTE 2 0.132 R7C9A.Q1 to R7C9A.A1 DecimalStrobeGenerator/Counter_0 CTOF_DEL --- 0.101 R7C9A.A1 to R7C9A.F1 DecimalStrobeGenerator/SLICE_40 ROUTE 1 0.000 R7C9A.F1 to R7C9A.DI1 DecimalStrobeGenerator/Counter_23_N_146_0 (to Clock14MHz) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to DecimalStrobeGenerator/SLICE_40: Name Fanout Delay (ns) Site Resource ROUTE 56 1.216 OSC.OSC to R7C9A.CLK Clock14MHz -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to DecimalStrobeGenerator/SLICE_40: Name Fanout Delay (ns) Site Resource ROUTE 56 1.216 OSC.OSC to R7C9A.CLK Clock14MHz -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DecimalStrobeGenerator/Counter_i5 (from Clock14MHz +) Destination: FF Data in DecimalStrobeGenerator/Counter_i5 (to Clock14MHz +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay DecimalStrobeGenerator/SLICE_36 to DecimalStrobeGenerator/SLICE_36 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path DecimalStrobeGenerator/SLICE_36 to DecimalStrobeGenerator/SLICE_36: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R7C9D.CLK to R7C9D.Q0 DecimalStrobeGenerator/SLICE_36 (from Clock14MHz) ROUTE 2 0.132 R7C9D.Q0 to R7C9D.A0 DecimalStrobeGenerator/Counter_5 CTOF_DEL --- 0.101 R7C9D.A0 to R7C9D.F0 DecimalStrobeGenerator/SLICE_36 ROUTE 1 0.000 R7C9D.F0 to R7C9D.DI0 DecimalStrobeGenerator/Counter_23_N_146_5 (to Clock14MHz) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to DecimalStrobeGenerator/SLICE_36: Name Fanout Delay (ns) Site Resource ROUTE 56 1.216 OSC.OSC to R7C9D.CLK Clock14MHz -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to DecimalStrobeGenerator/SLICE_36: Name Fanout Delay (ns) Site Resource ROUTE 56 1.216 OSC.OSC to R7C9D.CLK Clock14MHz -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Report Summary -------------- ---------------------------------------------------------------------------- Preference(MIN Delays) | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY NET "Clock14MHz" 14.000112 | | | MHz ; | 0.000 ns| 0.303 ns| 1 | | | ---------------------------------------------------------------------------- All preferences were met. Clock Domains Analysis ------------------------ Found 1 clocks: Clock Domain: Clock14MHz Source: OSCH_inst.OSC Loads: 56 Covered under: FREQUENCY NET "Clock14MHz" 14.000112 MHz ; Timing summary (Hold): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 1827 paths, 1 nets, and 641 connections (100.00% coverage) Timing summary (Setup and Hold): --------------- Timing errors: 0 (setup), 0 (hold) Score: 0 (setup), 0 (hold) Cumulative negative slack: 0 (0+0)