Synthesis and Ngdbuild  Report
synthesis:  version Diamond (64-bit) 3.12.1.454

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Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
Sun Feb 12 09:58:02 2023


Command Line:  synthesis -f Kurs09_RevealTest_lattice.synproj -gui -msgset D:/Lattice/Kurs09/promote.xml 

Synthesis options:
The -a option is MachXO2.
The -s option is 4.
The -t option is TQFP100.
The -d option is LCMXO2-1200HC.
Using package TQFP100.
Using performance grade 4.
                                                          

##########################################################

### Lattice Family : MachXO2

### Device  : LCMXO2-1200HC

### Package : TQFP100

### Speed   : 4

##########################################################

                                                          

INFO - synthesis: User-Selected Strategy Settings
Optimization goal = Balanced
Top-level module name = top.
Target frequency = 200.000000 MHz.
Maximum fanout = 1000.
Timing path count = 3
BRAM utilization = 100.000000 %
DSP usage = true
DSP utilization = 100.000000 %
fsm_encoding_style = auto
resolve_mixed_drivers = 0
fix_gated_clocks = 1

Mux style = Auto
Use Carry Chain = true
carry_chain_length = 0
Loop Limit = 1950.
Use IO Insertion = TRUE
Use IO Reg = AUTO

Resource Sharing = TRUE
Propagate Constants = TRUE
Remove Duplicate Registers = TRUE
force_gsr = auto
ROM style = auto
RAM style = auto
The -comp option is FALSE.
The -syn option is FALSE.
-p D:/Lattice/diamond/3.12/ispfpga/xo2c00/data (searchpath added)
-p D:/Lattice/Kurs09/RevealTest (searchpath added)
-p D:/Lattice/Kurs09 (searchpath added)
-p D:/Lattice/Kurs09/RevealTest/reveal_workspace/reveal (searchpath added)
Key file = D:/Lattice/diamond/3.12/module/reveal/document/reveal_test.dat
File D:/Lattice/diamond/3.12/module/reveal/src/ertl/ertl.v is encrypted

File D:/Lattice/diamond/3.12/module/reveal/src/rvl_j2w_module/rvl_j2w_module.v is encrypted

File D:/Lattice/diamond/3.12/module/reveal/src/ertl/JTAG_SOFT.v is encrypted

Verilog design file = D:/Lattice/diamond/3.12/cae_library/synthesis/verilog/pmi_def.v
Verilog design file = D:/Lattice/diamond/3.12/module/reveal/src/ertl/ertl.v
Verilog design file = D:/Lattice/diamond/3.12/module/reveal/src/rvl_j2w_module/rvl_j2w_module.v
Verilog design file = D:/Lattice/diamond/3.12/module/reveal/src/rvl_j2w_module/wb2sci.v
Verilog design file = D:/Lattice/diamond/3.12/module/reveal/src/ertl/JTAG_SOFT.v
Verilog design file = D:/Lattice/Kurs09/RevealTest/reveal_workspace/tmpreveal/top_la0_trig_gen.v
Verilog design file = D:/Lattice/Kurs09/RevealTest/reveal_workspace/tmpreveal/top_la0_gen.v
Verilog design file = D:/Lattice/Kurs09/RevealTest/reveal_workspace/tmpreveal/top_rvl.v
NGD file = Kurs09_RevealTest.ngd
-sdc option: SDC file input is D:/Lattice/Kurs09/RevealTest/source/kurs09.ldc.
-lpf option: Output file option is ON.
Hardtimer checking is enabled (default). The -dt option is not used.
The -r option is OFF. [ Remove LOC Properties is OFF. ]
Technology check ok...

Analyzing Verilog file D:/Lattice/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
Compile design.
Compile Design Begin
Analyzing Verilog file d:/lattice/diamond/3.12/cae_library/synthesis/verilog/pmi_def.v. VERI-1482
Analyzing Verilog file d:/lattice/diamond/3.12/module/reveal/src/rvl_j2w_module/wb2sci.v. VERI-1482
Analyzing Verilog file d:/lattice/kurs09/revealtest/reveal_workspace/tmpreveal/top_la0_trig_gen.v. VERI-1482
Analyzing Verilog file d:/lattice/kurs09/revealtest/reveal_workspace/tmpreveal/top_la0_gen.v. VERI-1482
Analyzing Verilog file d:/lattice/kurs09/revealtest/reveal_workspace/tmpreveal/top_rvl.v. VERI-1482
Analyzing Verilog file .__ydixd0.v. VERI-1482
Top module name (Verilog): top
Loading NGL library 'D:/Lattice/diamond/3.12/ispfpga/xo2c00a/data/xo2alib.ngl'...
Loading NGL library 'D:/Lattice/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
Loading NGL library 'D:/Lattice/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
Loading NGL library 'D:/Lattice/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
Loading device for application map from file 'xo2c1200.nph' in environment: D:/Lattice/diamond/3.12/ispfpga.
Package Status:                     Final          Version 1.44.
Top-level module name = top.



WARNING - synthesis: PMI modules used in the design, GSR inference is disabled, please infer GSR in 'Map Design' stage if required.
######## GSR will not be inferred because the gsr attribute is present in either the top or sub module or because an instantiated GSR is present.
Writing LPF file Kurs09_RevealTest.lpf.
top_prim.v file will not be written because encrypted design file is being used

Results of NGD DRC are available in top_drc.log.
Loading NGL library 'D:/Lattice/diamond/3.12/ispfpga/xo2c00a/data/xo2alib.ngl'...
Loading NGL library 'D:/Lattice/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
Loading NGL library 'D:/Lattice/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
Loading NGL library 'D:/Lattice/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
Loading NGL library 'D:/Lattice/diamond/3.12/ispfpga/data/neoprims.ngl'...
Loading NGL library 'D:/Lattice/diamond/3.12/ispfpga/data/neomacro.ngl'...
Loading NGO design 'lngotmp/pmi_ram_dpxbnonesadr11211211401afe.ngo'...
Loading NGO design 'lngotmp/pmi_distributed_dpramxbnoner84168b99897.ngo'...
Loading NGO design 'lngotmp/pmi_ram_dpxbnonesadr25825625825611ac9918.ngo'...
Logic has been added to the IP to support JTAG capability.
Loading NGO design 'D:/Lattice/diamond/3.12/ispfpga/xo2c00/data/xo2chub.ngl'...
WARNING - synthesis: logical net 'top_reveal_coretop_instance/jupdate[0]' has no load.
WARNING - synthesis: logical net 'xo2chub/tdoa' has no load.
WARNING - synthesis: logical net 'xo2chub/cdn' has no load.
WARNING - synthesis: logical net 'xo2chub/ip_enable[15]' has no load.
WARNING - synthesis: logical net 'xo2chub/genblk7.un1_jtagf_u' has no load.
WARNING - synthesis: logical net 'xo2chub/genblk7.un1_jtagf_u_1' has no load.
WARNING - synthesis: DRC complete with 6 warnings.
All blocks are expanded and NGD expansion is successful.
Writing NGD file Kurs09_RevealTest.ngd.

################### Begin Area Report (top)######################
Number of register bits => 492 of 1520 (32 % )
CCU2D => 87
FD1P3AX => 18
FD1P3BX => 43
FD1P3DX => 293
FD1S3BX => 42
FD1S3DX => 96
GSR => 1
IB => 1
INV => 1
L6MUX21 => 10
LUT4 => 777
OB => 16
OSCH => 1
PFUMX => 52
pmi_distributed_dpramXbnoner84168b99897 => 1
pmi_ram_dpXbnonesadr11211211401afe => 1
pmi_ram_dpXbnonesadr25825625825611ac9918 => 1
################### End Area Report ##################

################### Begin BlackBox Report ######################
TSALL => 1
jtagconn16 => 1
################### End BlackBox Report ##################

################### Begin Clock Report ######################
Clock Nets
Number of Clocks: 2
  Net : Clock14MHz, loads : 305
  Net : top_reveal_coretop_instance/jtck[0], loads : 1
Clock Enable Nets
Number of Clock Enables: 46
Top 10 highest fanout Clock Enables:
  Net : top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jtck_N_283_enable_81, loads : 40
  Net : top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jtck_N_283_enable_78, loads : 35
  Net : top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d, loads : 30
  Net : top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jtck_N_283_enable_125, loads : 27
  Net : top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jtck_N_283_enable_39, loads : 16
  Net : top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr[2], loads : 16
  Net : top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jtck_N_283_enable_35, loads : 16
  Net : top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout_int_24__N_1135, loads : 9
  Net : top_reveal_coretop_instance/top_la0_inst_0/tm_u/clk[0]_N_keep_enable_86, loads : 8
  Net : top_reveal_coretop_instance/top_la0_inst_0/tm_u/clk[0]_N_keep_enable_101, loads : 8
Highest fanout non-clock nets
Top 10 highest fanout non-clock nets:
  Net : top_reveal_coretop_instance/jtck_N_283, loads : 193
  Net : top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jrstn_N_281, loads : 187
  Net : top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/n10749, loads : 170
  Net : DisplayMultiplex0/StrobeGenerator0/Reset_N_34, loads : 113
  Net : top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr[0], loads : 51
  Net : top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jtck_N_283_enable_81, loads : 49
  Net : top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/n10741, loads : 45
  Net : top_reveal_coretop_instance/ip_enable[0], loads : 44
  Net : top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr[1], loads : 37
  Net : top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jtck_N_283_enable_78, loads : 35
################### End Clock Report ##################

Timing Report Summary
--------------
--------------------------------------------------------------------------------
Constraint                              |   Constraint|       Actual|Levels
--------------------------------------------------------------------------------
                                        |             |             |
create_clock -period 5.000000 -name     |             |             |
clk500 [get_nets                        |             |             |
\top_reveal_coretop_instance/jtck[0]]   |  200.000 MHz|   61.843 MHz|    11 *
                                        |             |             |
create_clock -period 71.428001          |             |             |
-waveform { 0.000000 35.714001 } -name  |             |             |
Zegar [ get_nets { Clock14MHz } ]       |   14.000 MHz|   73.932 MHz|     9  
                                        |             |             |
--------------------------------------------------------------------------------


1 constraints not met.


Peak Memory Usage: 74.098  MB

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Elapsed CPU time for LSE flow : 3.641  secs
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