PAR: Place And Route Diamond (64-bit) 3.12.1.454.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
Sun Feb 12 09:58:08 2023

D:/Lattice/diamond/3.12/ispfpga\bin\nt64\par -f Kurs09_RevealTest.p2t
Kurs09_RevealTest_map.ncd Kurs09_RevealTest.dir Kurs09_RevealTest.prf -gui
-msgset D:/Lattice/Kurs09/promote.xml


Preference file: Kurs09_RevealTest.prf.

Cost Table Summary
Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
----------   --------     -----        ------       -----------  -----------  ----         ------
5_1   *      0            -1.559       225868       0.219        0            13           Completed
* : Design saved.

Total (real) run time for 1-seed: 13 secs 

par done!

Note: user must run 'Trace' for timing closure signoff.

Lattice Place and Route Report for Design "Kurs09_RevealTest_map.ncd"
Sun Feb 12 09:58:08 2023


Best Par Run
PAR: Place And Route Diamond (64-bit) 3.12.1.454.
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/Lattice/Kurs09/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 Kurs09_RevealTest_map.ncd Kurs09_RevealTest.dir/5_1.ncd Kurs09_RevealTest.prf
Preference file: Kurs09_RevealTest.prf.
Placement level-cost: 5-1.
Routing Iterations: 6

Loading design for application par from file Kurs09_RevealTest_map.ncd.
Design name: top
NCD version: 3.3
Vendor:      LATTICE
Device:      LCMXO2-1200HC
Package:     TQFP100
Performance: 4
Loading device for application par from file 'xo2c1200.nph' in environment: D:/Lattice/diamond/3.12/ispfpga.
Package Status:                     Final          Version 1.44.
Performance Hardware Data Status:   Final          Version 34.4.
License checked out.


Ignore Preference Error(s):  True

Device utilization summary:

   PIO (prelim)   17+4(JTAG)/108     19% used
                  17+4(JTAG)/80      26% bonded

   SLICE            505/640          78% used

   GSR                1/1           100% used
   OSC                1/1           100% used
   JTAG               1/1           100% used
   EBR                3/7            42% used


INFO: Design contains EBR with ASYNC Reset Mode that has a limitation: The use of the EBR block asynchronous reset requires that certain timing be met between the clock and the reset within the memory block. See the device specific data sheet for additional details.
Number of Signals: 1611
Number of Connections: 4513

Pin Constraint Summary:
   17 out of 17 pins locked (100% locked).

The following 2 signals are selected to use the primary clock routing resources:
    Clock14MHz (driver: OSCH_inst, clk load #: 186)
    jtaghub16_jtck (driver: xo2chub/genblk7.jtagf_u, clk load #: 150)


The following 8 signals are selected to use the secondary clock routing resources:
    jtaghub16_jrstn (driver: xo2chub/genblk7.jtagf_u, clk load #: 0, sr load #: 142, ce load #: 0)
    top_reveal_coretop_instance/top_la0_inst_0/n10749 (driver: top_reveal_coretop_instance/top_la0_inst_0/SLICE_542, clk load #: 0, sr load #: 115, ce load #: 0)
    top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jtck_N_283_enable_78 (driver: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_540, clk load #: 0, sr load #: 0, ce load #: 25)
    CountEnable (driver: CountStrobeGenerator/SLICE_110, clk load #: 0, sr load #: 0, ce load #: 17)
    top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jtck_N_283_enable_125 (driver: SLICE_161, clk load #: 0, sr load #: 0, ce load #: 15)
    jtaghub16_ip_enable0 (driver: SLICE_35, clk load #: 0, sr load #: 0, ce load #: 14)
    sample_en_d (driver: SLICE_167, clk load #: 0, sr load #: 0, ce load #: 13)
    top_reveal_coretop_instance/top_la0_inst_0/jtck_N_283_enable_149 (driver: top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_505, clk load #: 0, sr load #: 0, ce load #: 13)

Signal Reset_c is selected as Global Set/Reset.
Starting Placer Phase 0.
.........
Finished Placer Phase 0.  REAL time: 0 secs 

Starting Placer Phase 1.
....................
Placer score = 251799.
Finished Placer Phase 1.  REAL time: 7 secs 

Starting Placer Phase 2.
.
Placer score =  250425
Finished Placer Phase 2.  REAL time: 8 secs 



Clock Report

Global Clock Resources:
  CLK_PIN    : 0 out of 8 (0%)
  PLL        : 0 out of 1 (0%)
  DCM        : 0 out of 2 (0%)
  DCC        : 0 out of 8 (0%)

Global Clocks:
  PRIMARY "Clock14MHz" from OSC on comp "OSCH_inst" on site "OSC", clk load = 186
  PRIMARY "jtaghub16_jtck" from JTCK on comp "xo2chub/genblk7.jtagf_u" on site "JTAG", clk load = 150
  SECONDARY "jtaghub16_jrstn" from JRSTN on comp "xo2chub/genblk7.jtagf_u" on site "JTAG", clk load = 0, ce load = 0, sr load = 142
  SECONDARY "top_reveal_coretop_instance/top_la0_inst_0/n10749" from F0 on comp "top_reveal_coretop_instance/top_la0_inst_0/SLICE_542" on site "R7C14D", clk load = 0, ce load = 0, sr load = 115
  SECONDARY "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jtck_N_283_enable_78" from F0 on comp "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_540" on site "R7C12C", clk load = 0, ce load = 25, sr load = 0
  SECONDARY "CountEnable" from Q0 on comp "CountStrobeGenerator/SLICE_110" on site "R10C6C", clk load = 0, ce load = 17, sr load = 0
  SECONDARY "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jtck_N_283_enable_125" from F1 on comp "SLICE_161" on site "R7C12A", clk load = 0, ce load = 15, sr load = 0
  SECONDARY "jtaghub16_ip_enable0" from Q0 on comp "SLICE_35" on site "R10C5A", clk load = 0, ce load = 14, sr load = 0
  SECONDARY "sample_en_d" from Q0 on comp "SLICE_167" on site "R8C21A", clk load = 0, ce load = 13, sr load = 0
  SECONDARY "top_reveal_coretop_instance/top_la0_inst_0/jtck_N_283_enable_149" from F0 on comp "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_505" on site "R7C12B", clk load = 0, ce load = 13, sr load = 0

  PRIMARY  : 2 out of 8 (25%)
  SECONDARY: 8 out of 8 (100%)

Edge Clocks:
  No edge clock selected.




I/O Usage Summary (final):
   17 + 4(JTAG) out of 108 (19.4%) PIO sites used.
   17 + 4(JTAG) out of 80 (26.3%) bonded PIO sites used.
   Number of PIO comps: 17; differential: 0.
   Number of Vref pins used: 0.

I/O Bank Usage Summary:
+----------+----------------+------------+-----------+
| I/O Bank | Usage          | Bank Vccio | Bank Vref |
+----------+----------------+------------+-----------+
| 0        | 0 / 19 (  0%)  | -          | -         |
| 1        | 1 / 21 (  4%)  | 3.3V       | -         |
| 2        | 14 / 20 ( 70%) | 3.3V       | -         |
| 3        | 2 / 20 ( 10%)  | 3.3V       | -         |
+----------+----------------+------------+-----------+

Total placer CPU time: 7 secs 

Dumping design to file Kurs09_RevealTest.dir/5_1.ncd.

0 connections routed; 4513 unrouted.
Starting router resource preassignment

Completed router resource preassignment. Real time: 9 secs 

Start NBR router at 09:58:17 02/12/23

*****************************************************************
Info: NBR allows conflicts(one node used by more than one signal)
      in the earlier iterations. In each iteration, it tries to  
      solve the conflicts while keeping the critical connections 
      routed as short as possible. The routing process is said to
      be completed when no conflicts exist and all connections   
      are routed.                                                
Note: NBR uses a different method to calculate timing slacks. The
      worst slack and total negative slack may not be the same as
      that in TRCE report. You should always run TRCE to verify  
      your design.                                               
*****************************************************************

Start NBR special constraint process at 09:58:17 02/12/23

Start NBR section for initial routing at 09:58:17 02/12/23
Level 1, iteration 1
17(0.02%) conflicts; 3221(71.37%) untouched conns; 95348 (nbr) score; 
Estimated worst slack/total negative slack<setup>: -1.109ns/-95.348ns; real time: 9 secs 
Level 2, iteration 1
62(0.07%) conflicts; 2914(64.57%) untouched conns; 42281 (nbr) score; 
Estimated worst slack/total negative slack<setup>: -1.259ns/-42.281ns; real time: 9 secs 
Level 3, iteration 1
64(0.08%) conflicts; 1815(40.22%) untouched conns; 66880 (nbr) score; 
Estimated worst slack/total negative slack<setup>: -1.282ns/-66.881ns; real time: 10 secs 
Level 4, iteration 1
89(0.10%) conflicts; 0(0.00%) untouched conn; 68069 (nbr) score; 
Estimated worst slack/total negative slack<setup>: -1.310ns/-68.069ns; real time: 10 secs 

Info: Initial congestion level at 75% usage is 0
Info: Initial congestion area  at 75% usage is 0 (0.00%)

Start NBR section for normal routing at 09:58:18 02/12/23
Level 1, iteration 1
25(0.03%) conflicts; 91(2.02%) untouched conns; 68482 (nbr) score; 
Estimated worst slack/total negative slack<setup>: -1.302ns/-68.482ns; real time: 10 secs 
Level 1, iteration 2
21(0.02%) conflicts; 91(2.02%) untouched conns; 67108 (nbr) score; 
Estimated worst slack/total negative slack<setup>: -1.302ns/-67.108ns; real time: 10 secs 
Level 2, iteration 1
16(0.02%) conflicts; 93(2.06%) untouched conns; 67879 (nbr) score; 
Estimated worst slack/total negative slack<setup>: -1.310ns/-67.879ns; real time: 11 secs 
Level 3, iteration 1
18(0.02%) conflicts; 83(1.84%) untouched conns; 72631 (nbr) score; 
Estimated worst slack/total negative slack<setup>: -1.500ns/-72.631ns; real time: 11 secs 
Level 3, iteration 2
12(0.01%) conflicts; 82(1.82%) untouched conns; 76414 (nbr) score; 
Estimated worst slack/total negative slack<setup>: -1.559ns/-76.415ns; real time: 11 secs 
Level 4, iteration 1
42(0.05%) conflicts; 0(0.00%) untouched conn; 74363 (nbr) score; 
Estimated worst slack/total negative slack<setup>: -1.500ns/-74.363ns; real time: 11 secs 
Level 4, iteration 2
29(0.03%) conflicts; 0(0.00%) untouched conn; 77314 (nbr) score; 
Estimated worst slack/total negative slack<setup>: -1.559ns/-77.315ns; real time: 11 secs 
Level 4, iteration 3
16(0.02%) conflicts; 0(0.00%) untouched conn; 75866 (nbr) score; 
Estimated worst slack/total negative slack<setup>: -1.500ns/-75.866ns; real time: 11 secs 
Level 4, iteration 4
8(0.01%) conflicts; 0(0.00%) untouched conn; 75866 (nbr) score; 
Estimated worst slack/total negative slack<setup>: -1.500ns/-75.866ns; real time: 11 secs 
Level 4, iteration 5
5(0.01%) conflicts; 0(0.00%) untouched conn; 86140 (nbr) score; 
Estimated worst slack/total negative slack<setup>: -1.559ns/-86.141ns; real time: 11 secs 
Level 4, iteration 6
5(0.01%) conflicts; 0(0.00%) untouched conn; 86140 (nbr) score; 
Estimated worst slack/total negative slack<setup>: -1.559ns/-86.141ns; real time: 11 secs 
Level 4, iteration 7
3(0.00%) conflicts; 0(0.00%) untouched conn; 85920 (nbr) score; 
Estimated worst slack/total negative slack<setup>: -1.559ns/-85.921ns; real time: 11 secs 
Level 4, iteration 8
4(0.00%) conflicts; 0(0.00%) untouched conn; 85920 (nbr) score; 
Estimated worst slack/total negative slack<setup>: -1.559ns/-85.921ns; real time: 11 secs 
Level 4, iteration 9
1(0.00%) conflict; 0(0.00%) untouched conn; 86916 (nbr) score; 
Estimated worst slack/total negative slack<setup>: -1.559ns/-86.917ns; real time: 11 secs 
Level 4, iteration 10
1(0.00%) conflict; 0(0.00%) untouched conn; 86916 (nbr) score; 
Estimated worst slack/total negative slack<setup>: -1.559ns/-86.917ns; real time: 11 secs 
Level 4, iteration 11
1(0.00%) conflict; 0(0.00%) untouched conn; 86916 (nbr) score; 
Estimated worst slack/total negative slack<setup>: -1.559ns/-86.917ns; real time: 11 secs 
Level 4, iteration 12
1(0.00%) conflict; 0(0.00%) untouched conn; 86916 (nbr) score; 
Estimated worst slack/total negative slack<setup>: -1.559ns/-86.917ns; real time: 11 secs 
Level 4, iteration 13
1(0.00%) conflict; 0(0.00%) untouched conn; 86916 (nbr) score; 
Estimated worst slack/total negative slack<setup>: -1.559ns/-86.917ns; real time: 11 secs 
Level 4, iteration 14
2(0.00%) conflicts; 0(0.00%) untouched conn; 86916 (nbr) score; 
Estimated worst slack/total negative slack<setup>: -1.559ns/-86.917ns; real time: 11 secs 
Level 4, iteration 15
0(0.00%) conflict; 0(0.00%) untouched conn; 87173 (nbr) score; 
Estimated worst slack/total negative slack<setup>: -1.559ns/-87.174ns; real time: 12 secs 

Start NBR section for performance tuning (iteration 1) at 09:58:20 02/12/23
Level 4, iteration 1
3(0.00%) conflicts; 0(0.00%) untouched conn; 86133 (nbr) score; 
Estimated worst slack/total negative slack<setup>: -1.559ns/-86.134ns; real time: 12 secs 
Level 4, iteration 2
1(0.00%) conflict; 0(0.00%) untouched conn; 103408 (nbr) score; 
Estimated worst slack/total negative slack<setup>: -2.156ns/-103.408ns; real time: 12 secs 

Start NBR section for re-routing at 09:58:20 02/12/23
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 87173 (nbr) score; 
Estimated worst slack/total negative slack<setup>: -1.559ns/-87.174ns; real time: 12 secs 

Start NBR section for post-routing at 09:58:20 02/12/23

End NBR router with 0 unrouted connection

NBR Summary
-----------
  Number of unrouted connections : 0 (0.00%)
  Number of connections with timing violations : 119 (2.64%)
  Estimated worst slack<setup> : -1.559ns
  Timing score<setup> : 225868
-----------
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.



Total CPU time 12 secs 
Total REAL time: 13 secs 
Completely routed.
End of route.  4513 routed (100.00%); 0 unrouted.

Hold time timing score: 0, hold timing errors: 0

Timing score: 225868 

Dumping design to file Kurs09_RevealTest.dir/5_1.ncd.


All signals are completely routed.


PAR_SUMMARY::Run status = Completed
PAR_SUMMARY::Number of unrouted conns = 0
PAR_SUMMARY::Worst  slack<setup/<ns>> = -1.559
PAR_SUMMARY::Timing score<setup/<ns>> = 225.868
PAR_SUMMARY::Worst  slack<hold /<ns>> = 0.219
PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
PAR_SUMMARY::Number of errors = 0

Total CPU  time to completion: 12 secs 
Total REAL time to completion: 13 secs 

par done!

Note: user must run 'Trace' for timing closure signoff.

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.