Lattice Synthesis Timing Report
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Lattice Synthesis Timing Report, Version  
Sat Feb 11 15:35:22 2023

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
------------------
Design:     top
Constraint file: top_temp_lse.sdc 
Report level:    verbose report, limited to 3 items per constraint
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================================================================================
Constraint: create_clock -period 71.428001 -waveform { 0.000000 35.714001 } -name Zegar [ get_nets { Clock14MHz } ]
            927 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed:  The following path meets requirements by 64.424ns

 Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)

   Source:         FD1S3JX    CK             \DecimalStrobeGenerator/Counter_i0  (from Clock14MHz +)
   Destination:    FD1S3JX    PD             \DecimalStrobeGenerator/Counter_i0  (to Clock14MHz +)

   Delay:                   6.844ns  (28.1% logic, 71.9% route), 4 logic levels.

 Constraint Details:

      6.844ns data_path \DecimalStrobeGenerator/Counter_i0 to \DecimalStrobeGenerator/Counter_i0 meets
     71.428ns delay constraint less
      0.160ns L_S requirement (totaling 71.268ns) by 64.424ns

 Path Details: \DecimalStrobeGenerator/Counter_i0 to \DecimalStrobeGenerator/Counter_i0

   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
L_CO        ---     0.444             CK to Q              \DecimalStrobeGenerator/Counter_i0 (from Clock14MHz)
Route         2   e 1.198                                  \DecimalStrobeGenerator/Counter[0]
LUT4        ---     0.493              B to Z              \DecimalStrobeGenerator/i6_2_lut
Route         1   e 0.941                                  \DecimalStrobeGenerator/n30
LUT4        ---     0.493              C to Z              \DecimalStrobeGenerator/i20_4_lut
Route         1   e 0.941                                  \DecimalStrobeGenerator/n44
LUT4        ---     0.493              C to Z              \DecimalStrobeGenerator/i574_4_lut
Route        25   e 1.841                                  \DecimalStrobeGenerator/Counter_23__N_170
                  --------
                    6.844  (28.1% logic, 71.9% route), 4 logic levels.


Passed:  The following path meets requirements by 64.424ns

 Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)

   Source:         FD1S3JX    CK             \DecimalStrobeGenerator/Counter_i0  (from Clock14MHz +)
   Destination:    FD1S3AX    D              \DecimalStrobeGenerator/Strobe_13  (to Clock14MHz +)

   Delay:                   6.844ns  (28.1% logic, 71.9% route), 4 logic levels.

 Constraint Details:

      6.844ns data_path \DecimalStrobeGenerator/Counter_i0 to \DecimalStrobeGenerator/Strobe_13 meets
     71.428ns delay constraint less
      0.160ns L_S requirement (totaling 71.268ns) by 64.424ns

 Path Details: \DecimalStrobeGenerator/Counter_i0 to \DecimalStrobeGenerator/Strobe_13

   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
L_CO        ---     0.444             CK to Q              \DecimalStrobeGenerator/Counter_i0 (from Clock14MHz)
Route         2   e 1.198                                  \DecimalStrobeGenerator/Counter[0]
LUT4        ---     0.493              B to Z              \DecimalStrobeGenerator/i6_2_lut
Route         1   e 0.941                                  \DecimalStrobeGenerator/n30
LUT4        ---     0.493              C to Z              \DecimalStrobeGenerator/i20_4_lut
Route         1   e 0.941                                  \DecimalStrobeGenerator/n44
LUT4        ---     0.493              C to Z              \DecimalStrobeGenerator/i574_4_lut
Route        25   e 1.841                                  \DecimalStrobeGenerator/Counter_23__N_170
                  --------
                    6.844  (28.1% logic, 71.9% route), 4 logic levels.


Passed:  The following path meets requirements by 64.424ns

 Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)

   Source:         FD1S3JX    CK             \DecimalStrobeGenerator/Counter_i0  (from Clock14MHz +)
   Destination:    FD1S3JX    PD             \DecimalStrobeGenerator/Counter_i23  (to Clock14MHz +)

   Delay:                   6.844ns  (28.1% logic, 71.9% route), 4 logic levels.

 Constraint Details:

      6.844ns data_path \DecimalStrobeGenerator/Counter_i0 to \DecimalStrobeGenerator/Counter_i23 meets
     71.428ns delay constraint less
      0.160ns L_S requirement (totaling 71.268ns) by 64.424ns

 Path Details: \DecimalStrobeGenerator/Counter_i0 to \DecimalStrobeGenerator/Counter_i23

   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
L_CO        ---     0.444             CK to Q              \DecimalStrobeGenerator/Counter_i0 (from Clock14MHz)
Route         2   e 1.198                                  \DecimalStrobeGenerator/Counter[0]
LUT4        ---     0.493              B to Z              \DecimalStrobeGenerator/i6_2_lut
Route         1   e 0.941                                  \DecimalStrobeGenerator/n30
LUT4        ---     0.493              C to Z              \DecimalStrobeGenerator/i20_4_lut
Route         1   e 0.941                                  \DecimalStrobeGenerator/n44
LUT4        ---     0.493              C to Z              \DecimalStrobeGenerator/i574_4_lut
Route        25   e 1.841                                  \DecimalStrobeGenerator/Counter_23__N_170
                  --------
                    6.844  (28.1% logic, 71.9% route), 4 logic levels.

Report: 7.004 ns is the maximum delay for this constraint.


Timing Report Summary
--------------
--------------------------------------------------------------------------------
Constraint                              |   Constraint|       Actual|Levels
--------------------------------------------------------------------------------
                                        |             |             |
create_clock -period 71.428001          |             |             |
-waveform { 0.000000 35.714001 } -name  |             |             |
Zegar [ get_nets { Clock14MHz } ]       |    71.428 ns|     7.004 ns|     4  
                                        |             |             |
--------------------------------------------------------------------------------


All constraints were met.



Timing summary:
---------------

Timing errors: 0  Score: 0

Constraints cover  2535 paths, 268 nets, and 533 connections (69.0% coverage)


Peak memory: 59420672 bytes, TRCE: 0 bytes, DLYMAN: 0 bytes
CPU_TIME_REPORT: 0 secs