Lattice Synthesis Timing Report -------------------------------------------------------------------------------- Lattice Synthesis Timing Report, Version Mon Sep 04 21:18:34 2023 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Design: top Constraint file: top_temp_lse.sdc Report level: verbose report, limited to 3 items per constraint -------------------------------------------------------------------------------- ================================================================================ Constraint: create_clock -period 71.428001 -waveform { 0.000000 35.714001 } -name Clock [ get_nets { Clock } ] 745 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 64.831ns Logical Details: Cell type Pin type Cell name (clock net +/-) Source: FD1P3AX CK \Encoder1/Increment_o_39 (from Clock +) Destination: FD1S3AX D Counter1_i14 (to Clock +) Delay: 6.451ns (48.8% logic, 51.2% route), 11 logic levels. Constraint Details: 6.451ns data_path \Encoder1/Increment_o_39 to Counter1_i14 meets 71.428ns delay constraint less 0.146ns L_S requirement (totaling 71.282ns) by 64.831ns Path Details: \Encoder1/Increment_o_39 to Counter1_i14 Name Fanout Delay (ns) Pins Resource(Cell.Net) L_CO --- 0.403 CK to Q \Encoder1/Increment_o_39 (from Clock) Route 17 e 1.567 Increment1 A1_TO_FCO --- 0.752 A[2] to COUT add_197_1 Route 1 e 0.020 n1169 FCI_TO_FCO --- 0.143 CIN to COUT add_197_3 Route 1 e 0.020 n1170 FCI_TO_FCO --- 0.143 CIN to COUT add_197_5 Route 1 e 0.020 n1171 FCI_TO_FCO --- 0.143 CIN to COUT add_197_7 Route 1 e 0.020 n1172 FCI_TO_FCO --- 0.143 CIN to COUT add_197_9 Route 1 e 0.020 n1173 FCI_TO_FCO --- 0.143 CIN to COUT add_197_11 Route 1 e 0.020 n1174 FCI_TO_FCO --- 0.143 CIN to COUT add_197_13 Route 1 e 0.020 n1175 FCI_TO_FCO --- 0.143 CIN to COUT add_197_15 Route 1 e 0.020 n1176 FCI_TO_F --- 0.544 CIN to S[2] add_197_17 Route 1 e 0.788 n636 LUT4 --- 0.448 C to Z mux_183_i15_3_lut_4_lut_3_lut Route 1 e 0.788 Counter1_15__N_1[14] -------- 6.451 (48.8% logic, 51.2% route), 11 logic levels. Passed: The following path meets requirements by 64.831ns Logical Details: Cell type Pin type Cell name (clock net +/-) Source: FD1P3AX CK \Encoder2/Increment_o_39 (from Clock +) Destination: FD1S3AX D Counter2_i14 (to Clock +) Delay: 6.451ns (48.8% logic, 51.2% route), 11 logic levels. Constraint Details: 6.451ns data_path \Encoder2/Increment_o_39 to Counter2_i14 meets 71.428ns delay constraint less 0.146ns L_S requirement (totaling 71.282ns) by 64.831ns Path Details: \Encoder2/Increment_o_39 to Counter2_i14 Name Fanout Delay (ns) Pins Resource(Cell.Net) L_CO --- 0.403 CK to Q \Encoder2/Increment_o_39 (from Clock) Route 17 e 1.567 Increment2 A1_TO_FCO --- 0.752 A[2] to COUT add_201_1 Route 1 e 0.020 n1181 FCI_TO_FCO --- 0.143 CIN to COUT add_201_3 Route 1 e 0.020 n1182 FCI_TO_FCO --- 0.143 CIN to COUT add_201_5 Route 1 e 0.020 n1183 FCI_TO_FCO --- 0.143 CIN to COUT add_201_7 Route 1 e 0.020 n1184 FCI_TO_FCO --- 0.143 CIN to COUT add_201_9 Route 1 e 0.020 n1185 FCI_TO_FCO --- 0.143 CIN to COUT add_201_11 Route 1 e 0.020 n1186 FCI_TO_FCO --- 0.143 CIN to COUT add_201_13 Route 1 e 0.020 n1187 FCI_TO_FCO --- 0.143 CIN to COUT add_201_15 Route 1 e 0.020 n1188 FCI_TO_F --- 0.544 CIN to S[2] add_201_17 Route 1 e 0.788 n670 LUT4 --- 0.448 C to Z \Encoder2/EdgeDetector_inst/mux_189_i15_3_lut_4_lut_3_lut Route 1 e 0.788 Counter2_15__N_19[14] -------- 6.451 (48.8% logic, 51.2% route), 11 logic levels. Passed: The following path meets requirements by 64.994ns Logical Details: Cell type Pin type Cell name (clock net +/-) Source: FD1P3AX CK \Encoder1/Increment_o_39 (from Clock +) Destination: FD1S3AX D Counter1_i12 (to Clock +) Delay: 6.288ns (47.8% logic, 52.2% route), 10 logic levels. Constraint Details: 6.288ns data_path \Encoder1/Increment_o_39 to Counter1_i12 meets 71.428ns delay constraint less 0.146ns L_S requirement (totaling 71.282ns) by 64.994ns Path Details: \Encoder1/Increment_o_39 to Counter1_i12 Name Fanout Delay (ns) Pins Resource(Cell.Net) L_CO --- 0.403 CK to Q \Encoder1/Increment_o_39 (from Clock) Route 17 e 1.567 Increment1 A1_TO_FCO --- 0.752 A[2] to COUT add_197_1 Route 1 e 0.020 n1169 FCI_TO_FCO --- 0.143 CIN to COUT add_197_3 Route 1 e 0.020 n1170 FCI_TO_FCO --- 0.143 CIN to COUT add_197_5 Route 1 e 0.020 n1171 FCI_TO_FCO --- 0.143 CIN to COUT add_197_7 Route 1 e 0.020 n1172 FCI_TO_FCO --- 0.143 CIN to COUT add_197_9 Route 1 e 0.020 n1173 FCI_TO_FCO --- 0.143 CIN to COUT add_197_11 Route 1 e 0.020 n1174 FCI_TO_FCO --- 0.143 CIN to COUT add_197_13 Route 1 e 0.020 n1175 FCI_TO_F --- 0.544 CIN to S[2] add_197_15 Route 1 e 0.788 n638 LUT4 --- 0.448 C to Z i511_2_lut_3_lut Route 1 e 0.788 Counter1_15__N_1[12] -------- 6.288 (47.8% logic, 52.2% route), 10 logic levels. Report: 6.597 ns is the maximum delay for this constraint. Timing Report Summary -------------- -------------------------------------------------------------------------------- Constraint | Constraint| Actual|Levels -------------------------------------------------------------------------------- | | | create_clock -period 71.428001 | | | -waveform { 0.000000 35.714001 } -name | | | Clock [ get_nets { Clock } ] | 71.428 ns| 6.597 ns| 11 | | | -------------------------------------------------------------------------------- All constraints were met. Timing summary: --------------- Timing errors: 0 Score: 0 Constraints cover 1082 paths, 184 nets, and 402 connections (63.8% coverage) Peak memory: 58695680 bytes, TRCE: 757760 bytes, DLYMAN: 0 bytes CPU_TIME_REPORT: 0 secs