Place & Route TRACE Report

Loading design for application trce from file enkoder_impl1.ncd.
Design name: top
NCD version: 3.3
Vendor:      LATTICE
Device:      LCMXO2-1200HC
Package:     TQFP100
Performance: 5
Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status:                     Final          Version 1.44.
Performance Hardware Data Status:   Final          Version 34.4.
Setup and Hold Report

--------------------------------------------------------------------------------
Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
Mon Sep 04 21:30:27 2023

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
------------------
Command line:    trce -v 10 -gt -sethld -sp 5 -sphld m -o Enkoder_impl1.twr -gui -msgset C:/Lattice/Kurs14/promote.xml Enkoder_impl1.ncd Enkoder_impl1.prf 
Design file:     enkoder_impl1.ncd
Preference file: enkoder_impl1.prf
Device,speed:    LCMXO2-1200HC,5
Report level:    verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------

Preference Summary

  • FREQUENCY NET "Clock" 14.000112 MHz (0 errors)
  • 955 items scored, 0 timing errors detected. Report: 167.757MHz is the maximum frequency for this preference. BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- Derating parameters ------------------- Temperature: 85 C Voltage: 3.300 V ================================================================================ Preference: FREQUENCY NET "Clock" 14.000112 MHz ; 955 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 65.467ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DisplayMultiplex_inst/StrobeGenerator0/Counter_i0 (from Clock +) Destination: FF Data in DisplayMultiplex_inst/StrobeGenerator0/Counter_i8 (to Clock +) FF DisplayMultiplex_inst/StrobeGenerator0/Counter_i7 Delay: 5.713ns (30.9% logic, 69.1% route), 4 logic levels. Constraint Details: 5.713ns physical path delay DisplayMultiplex_inst/StrobeGenerator0/SLICE_5 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_6 meets 71.428ns delay constraint less 0.000ns skew and 0.248ns LSR_SET requirement (totaling 71.180ns) by 65.467ns Physical Path Details: Data path DisplayMultiplex_inst/StrobeGenerator0/SLICE_5 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_6: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R4C12A.CLK to R4C12A.Q1 DisplayMultiplex_inst/StrobeGenerator0/SLICE_5 (from Clock) ROUTE 2 1.369 R4C12A.Q1 to R7C12C.A1 DisplayMultiplex_inst/StrobeGenerator0/Counter_0 CTOF_DEL --- 0.452 R7C12C.A1 to R7C12C.F1 SLICE_55 ROUTE 1 0.937 R7C12C.F1 to R5C12A.A0 DisplayMultiplex_inst/StrobeGenerator0/n18_adj_157 CTOF_DEL --- 0.452 R5C12A.A0 to R5C12A.F0 DisplayMultiplex_inst/StrobeGenerator0/SLICE_70 ROUTE 1 0.269 R5C12A.F0 to R5C12B.D0 DisplayMultiplex_inst/StrobeGenerator0/n26 CTOF_DEL --- 0.452 R5C12B.D0 to R5C12B.F0 DisplayMultiplex_inst/StrobeGenerator0/SLICE_40 ROUTE 9 1.373 R5C12B.F0 to R4C13A.LSR DisplayMultiplex_inst/StrobeGenerator0/Strobe_o_N_147 (to Clock) -------- 5.713 (30.9% logic, 69.1% route), 4 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to DisplayMultiplex_inst/StrobeGenerator0/SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 46 3.173 OSC.OSC to R4C12A.CLK Clock -------- 3.173 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to DisplayMultiplex_inst/StrobeGenerator0/SLICE_6: Name Fanout Delay (ns) Site Resource ROUTE 46 3.173 OSC.OSC to R4C13A.CLK Clock -------- 3.173 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 65.467ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DisplayMultiplex_inst/StrobeGenerator0/Counter_i0 (from Clock +) Destination: FF Data in DisplayMultiplex_inst/StrobeGenerator0/Counter_i12 (to Clock +) FF DisplayMultiplex_inst/StrobeGenerator0/Counter_i11 Delay: 5.713ns (30.9% logic, 69.1% route), 4 logic levels. Constraint Details: 5.713ns physical path delay DisplayMultiplex_inst/StrobeGenerator0/SLICE_5 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_9 meets 71.428ns delay constraint less 0.000ns skew and 0.248ns LSR_SET requirement (totaling 71.180ns) by 65.467ns Physical Path Details: Data path DisplayMultiplex_inst/StrobeGenerator0/SLICE_5 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_9: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R4C12A.CLK to R4C12A.Q1 DisplayMultiplex_inst/StrobeGenerator0/SLICE_5 (from Clock) ROUTE 2 1.369 R4C12A.Q1 to R7C12C.A1 DisplayMultiplex_inst/StrobeGenerator0/Counter_0 CTOF_DEL --- 0.452 R7C12C.A1 to R7C12C.F1 SLICE_55 ROUTE 1 0.937 R7C12C.F1 to R5C12A.A0 DisplayMultiplex_inst/StrobeGenerator0/n18_adj_157 CTOF_DEL --- 0.452 R5C12A.A0 to R5C12A.F0 DisplayMultiplex_inst/StrobeGenerator0/SLICE_70 ROUTE 1 0.269 R5C12A.F0 to R5C12B.D0 DisplayMultiplex_inst/StrobeGenerator0/n26 CTOF_DEL --- 0.452 R5C12B.D0 to R5C12B.F0 DisplayMultiplex_inst/StrobeGenerator0/SLICE_40 ROUTE 9 1.373 R5C12B.F0 to R4C13C.LSR DisplayMultiplex_inst/StrobeGenerator0/Strobe_o_N_147 (to Clock) -------- 5.713 (30.9% logic, 69.1% route), 4 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to DisplayMultiplex_inst/StrobeGenerator0/SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 46 3.173 OSC.OSC to R4C12A.CLK Clock -------- 3.173 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to DisplayMultiplex_inst/StrobeGenerator0/SLICE_9: Name Fanout Delay (ns) Site Resource ROUTE 46 3.173 OSC.OSC to R4C13C.CLK Clock -------- 3.173 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 65.467ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DisplayMultiplex_inst/StrobeGenerator0/Counter_i0 (from Clock +) Destination: FF Data in DisplayMultiplex_inst/StrobeGenerator0/Counter_i10 (to Clock +) FF DisplayMultiplex_inst/StrobeGenerator0/Counter_i9 Delay: 5.713ns (30.9% logic, 69.1% route), 4 logic levels. Constraint Details: 5.713ns physical path delay DisplayMultiplex_inst/StrobeGenerator0/SLICE_5 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_7 meets 71.428ns delay constraint less 0.000ns skew and 0.248ns LSR_SET requirement (totaling 71.180ns) by 65.467ns Physical Path Details: Data path DisplayMultiplex_inst/StrobeGenerator0/SLICE_5 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_7: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R4C12A.CLK to R4C12A.Q1 DisplayMultiplex_inst/StrobeGenerator0/SLICE_5 (from Clock) ROUTE 2 1.369 R4C12A.Q1 to R7C12C.A1 DisplayMultiplex_inst/StrobeGenerator0/Counter_0 CTOF_DEL --- 0.452 R7C12C.A1 to R7C12C.F1 SLICE_55 ROUTE 1 0.937 R7C12C.F1 to R5C12A.A0 DisplayMultiplex_inst/StrobeGenerator0/n18_adj_157 CTOF_DEL --- 0.452 R5C12A.A0 to R5C12A.F0 DisplayMultiplex_inst/StrobeGenerator0/SLICE_70 ROUTE 1 0.269 R5C12A.F0 to R5C12B.D0 DisplayMultiplex_inst/StrobeGenerator0/n26 CTOF_DEL --- 0.452 R5C12B.D0 to R5C12B.F0 DisplayMultiplex_inst/StrobeGenerator0/SLICE_40 ROUTE 9 1.373 R5C12B.F0 to R4C13B.LSR DisplayMultiplex_inst/StrobeGenerator0/Strobe_o_N_147 (to Clock) -------- 5.713 (30.9% logic, 69.1% route), 4 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to DisplayMultiplex_inst/StrobeGenerator0/SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 46 3.173 OSC.OSC to R4C12A.CLK Clock -------- 3.173 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to DisplayMultiplex_inst/StrobeGenerator0/SLICE_7: Name Fanout Delay (ns) Site Resource ROUTE 46 3.173 OSC.OSC to R4C13B.CLK Clock -------- 3.173 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 65.467ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DisplayMultiplex_inst/StrobeGenerator0/Counter_i0 (from Clock +) Destination: FF Data in DisplayMultiplex_inst/StrobeGenerator0/Counter_i13 (to Clock +) Delay: 5.713ns (30.9% logic, 69.1% route), 4 logic levels. Constraint Details: 5.713ns physical path delay DisplayMultiplex_inst/StrobeGenerator0/SLICE_5 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_4 meets 71.428ns delay constraint less 0.000ns skew and 0.248ns LSR_SET requirement (totaling 71.180ns) by 65.467ns Physical Path Details: Data path DisplayMultiplex_inst/StrobeGenerator0/SLICE_5 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_4: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R4C12A.CLK to R4C12A.Q1 DisplayMultiplex_inst/StrobeGenerator0/SLICE_5 (from Clock) ROUTE 2 1.369 R4C12A.Q1 to R7C12C.A1 DisplayMultiplex_inst/StrobeGenerator0/Counter_0 CTOF_DEL --- 0.452 R7C12C.A1 to R7C12C.F1 SLICE_55 ROUTE 1 0.937 R7C12C.F1 to R5C12A.A0 DisplayMultiplex_inst/StrobeGenerator0/n18_adj_157 CTOF_DEL --- 0.452 R5C12A.A0 to R5C12A.F0 DisplayMultiplex_inst/StrobeGenerator0/SLICE_70 ROUTE 1 0.269 R5C12A.F0 to R5C12B.D0 DisplayMultiplex_inst/StrobeGenerator0/n26 CTOF_DEL --- 0.452 R5C12B.D0 to R5C12B.F0 DisplayMultiplex_inst/StrobeGenerator0/SLICE_40 ROUTE 9 1.373 R5C12B.F0 to R4C13D.LSR DisplayMultiplex_inst/StrobeGenerator0/Strobe_o_N_147 (to Clock) -------- 5.713 (30.9% logic, 69.1% route), 4 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to DisplayMultiplex_inst/StrobeGenerator0/SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 46 3.173 OSC.OSC to R4C12A.CLK Clock -------- 3.173 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to DisplayMultiplex_inst/StrobeGenerator0/SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 46 3.173 OSC.OSC to R4C13D.CLK Clock -------- 3.173 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 65.686ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DisplayMultiplex_inst/StrobeGenerator0/Counter_i9 (from Clock +) Destination: FF Data in DisplayMultiplex_inst/StrobeGenerator0/Counter_i8 (to Clock +) FF DisplayMultiplex_inst/StrobeGenerator0/Counter_i7 Delay: 5.494ns (32.1% logic, 67.9% route), 4 logic levels. Constraint Details: 5.494ns physical path delay DisplayMultiplex_inst/StrobeGenerator0/SLICE_7 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_6 meets 71.428ns delay constraint less 0.000ns skew and 0.248ns LSR_SET requirement (totaling 71.180ns) by 65.686ns Physical Path Details: Data path DisplayMultiplex_inst/StrobeGenerator0/SLICE_7 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_6: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R4C13B.CLK to R4C13B.Q0 DisplayMultiplex_inst/StrobeGenerator0/SLICE_7 (from Clock) ROUTE 2 1.150 R4C13B.Q0 to R7C12C.C1 DisplayMultiplex_inst/StrobeGenerator0/Counter_9 CTOF_DEL --- 0.452 R7C12C.C1 to R7C12C.F1 SLICE_55 ROUTE 1 0.937 R7C12C.F1 to R5C12A.A0 DisplayMultiplex_inst/StrobeGenerator0/n18_adj_157 CTOF_DEL --- 0.452 R5C12A.A0 to R5C12A.F0 DisplayMultiplex_inst/StrobeGenerator0/SLICE_70 ROUTE 1 0.269 R5C12A.F0 to R5C12B.D0 DisplayMultiplex_inst/StrobeGenerator0/n26 CTOF_DEL --- 0.452 R5C12B.D0 to R5C12B.F0 DisplayMultiplex_inst/StrobeGenerator0/SLICE_40 ROUTE 9 1.373 R5C12B.F0 to R4C13A.LSR DisplayMultiplex_inst/StrobeGenerator0/Strobe_o_N_147 (to Clock) -------- 5.494 (32.1% logic, 67.9% route), 4 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to DisplayMultiplex_inst/StrobeGenerator0/SLICE_7: Name Fanout Delay (ns) Site Resource ROUTE 46 3.173 OSC.OSC to R4C13B.CLK Clock -------- 3.173 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to DisplayMultiplex_inst/StrobeGenerator0/SLICE_6: Name Fanout Delay (ns) Site Resource ROUTE 46 3.173 OSC.OSC to R4C13A.CLK Clock -------- 3.173 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 65.686ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DisplayMultiplex_inst/StrobeGenerator0/Counter_i9 (from Clock +) Destination: FF Data in DisplayMultiplex_inst/StrobeGenerator0/Counter_i12 (to Clock +) FF DisplayMultiplex_inst/StrobeGenerator0/Counter_i11 Delay: 5.494ns (32.1% logic, 67.9% route), 4 logic levels. Constraint Details: 5.494ns physical path delay DisplayMultiplex_inst/StrobeGenerator0/SLICE_7 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_9 meets 71.428ns delay constraint less 0.000ns skew and 0.248ns LSR_SET requirement (totaling 71.180ns) by 65.686ns Physical Path Details: Data path DisplayMultiplex_inst/StrobeGenerator0/SLICE_7 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_9: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R4C13B.CLK to R4C13B.Q0 DisplayMultiplex_inst/StrobeGenerator0/SLICE_7 (from Clock) ROUTE 2 1.150 R4C13B.Q0 to R7C12C.C1 DisplayMultiplex_inst/StrobeGenerator0/Counter_9 CTOF_DEL --- 0.452 R7C12C.C1 to R7C12C.F1 SLICE_55 ROUTE 1 0.937 R7C12C.F1 to R5C12A.A0 DisplayMultiplex_inst/StrobeGenerator0/n18_adj_157 CTOF_DEL --- 0.452 R5C12A.A0 to R5C12A.F0 DisplayMultiplex_inst/StrobeGenerator0/SLICE_70 ROUTE 1 0.269 R5C12A.F0 to R5C12B.D0 DisplayMultiplex_inst/StrobeGenerator0/n26 CTOF_DEL --- 0.452 R5C12B.D0 to R5C12B.F0 DisplayMultiplex_inst/StrobeGenerator0/SLICE_40 ROUTE 9 1.373 R5C12B.F0 to R4C13C.LSR DisplayMultiplex_inst/StrobeGenerator0/Strobe_o_N_147 (to Clock) -------- 5.494 (32.1% logic, 67.9% route), 4 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to DisplayMultiplex_inst/StrobeGenerator0/SLICE_7: Name Fanout Delay (ns) Site Resource ROUTE 46 3.173 OSC.OSC to R4C13B.CLK Clock -------- 3.173 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to DisplayMultiplex_inst/StrobeGenerator0/SLICE_9: Name Fanout Delay (ns) Site Resource ROUTE 46 3.173 OSC.OSC to R4C13C.CLK Clock -------- 3.173 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 65.686ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DisplayMultiplex_inst/StrobeGenerator0/Counter_i9 (from Clock +) Destination: FF Data in DisplayMultiplex_inst/StrobeGenerator0/Counter_i13 (to Clock +) Delay: 5.494ns (32.1% logic, 67.9% route), 4 logic levels. Constraint Details: 5.494ns physical path delay DisplayMultiplex_inst/StrobeGenerator0/SLICE_7 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_4 meets 71.428ns delay constraint less 0.000ns skew and 0.248ns LSR_SET requirement (totaling 71.180ns) by 65.686ns Physical Path Details: Data path DisplayMultiplex_inst/StrobeGenerator0/SLICE_7 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_4: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R4C13B.CLK to R4C13B.Q0 DisplayMultiplex_inst/StrobeGenerator0/SLICE_7 (from Clock) ROUTE 2 1.150 R4C13B.Q0 to R7C12C.C1 DisplayMultiplex_inst/StrobeGenerator0/Counter_9 CTOF_DEL --- 0.452 R7C12C.C1 to R7C12C.F1 SLICE_55 ROUTE 1 0.937 R7C12C.F1 to R5C12A.A0 DisplayMultiplex_inst/StrobeGenerator0/n18_adj_157 CTOF_DEL --- 0.452 R5C12A.A0 to R5C12A.F0 DisplayMultiplex_inst/StrobeGenerator0/SLICE_70 ROUTE 1 0.269 R5C12A.F0 to R5C12B.D0 DisplayMultiplex_inst/StrobeGenerator0/n26 CTOF_DEL --- 0.452 R5C12B.D0 to R5C12B.F0 DisplayMultiplex_inst/StrobeGenerator0/SLICE_40 ROUTE 9 1.373 R5C12B.F0 to R4C13D.LSR DisplayMultiplex_inst/StrobeGenerator0/Strobe_o_N_147 (to Clock) -------- 5.494 (32.1% logic, 67.9% route), 4 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to DisplayMultiplex_inst/StrobeGenerator0/SLICE_7: Name Fanout Delay (ns) Site Resource ROUTE 46 3.173 OSC.OSC to R4C13B.CLK Clock -------- 3.173 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to DisplayMultiplex_inst/StrobeGenerator0/SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 46 3.173 OSC.OSC to R4C13D.CLK Clock -------- 3.173 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 65.686ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DisplayMultiplex_inst/StrobeGenerator0/Counter_i9 (from Clock +) Destination: FF Data in DisplayMultiplex_inst/StrobeGenerator0/Counter_i10 (to Clock +) FF DisplayMultiplex_inst/StrobeGenerator0/Counter_i9 Delay: 5.494ns (32.1% logic, 67.9% route), 4 logic levels. Constraint Details: 5.494ns physical path delay DisplayMultiplex_inst/StrobeGenerator0/SLICE_7 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_7 meets 71.428ns delay constraint less 0.000ns skew and 0.248ns LSR_SET requirement (totaling 71.180ns) by 65.686ns Physical Path Details: Data path DisplayMultiplex_inst/StrobeGenerator0/SLICE_7 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_7: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R4C13B.CLK to R4C13B.Q0 DisplayMultiplex_inst/StrobeGenerator0/SLICE_7 (from Clock) ROUTE 2 1.150 R4C13B.Q0 to R7C12C.C1 DisplayMultiplex_inst/StrobeGenerator0/Counter_9 CTOF_DEL --- 0.452 R7C12C.C1 to R7C12C.F1 SLICE_55 ROUTE 1 0.937 R7C12C.F1 to R5C12A.A0 DisplayMultiplex_inst/StrobeGenerator0/n18_adj_157 CTOF_DEL --- 0.452 R5C12A.A0 to R5C12A.F0 DisplayMultiplex_inst/StrobeGenerator0/SLICE_70 ROUTE 1 0.269 R5C12A.F0 to R5C12B.D0 DisplayMultiplex_inst/StrobeGenerator0/n26 CTOF_DEL --- 0.452 R5C12B.D0 to R5C12B.F0 DisplayMultiplex_inst/StrobeGenerator0/SLICE_40 ROUTE 9 1.373 R5C12B.F0 to R4C13B.LSR DisplayMultiplex_inst/StrobeGenerator0/Strobe_o_N_147 (to Clock) -------- 5.494 (32.1% logic, 67.9% route), 4 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to DisplayMultiplex_inst/StrobeGenerator0/SLICE_7: Name Fanout Delay (ns) Site Resource ROUTE 46 3.173 OSC.OSC to R4C13B.CLK Clock -------- 3.173 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to DisplayMultiplex_inst/StrobeGenerator0/SLICE_7: Name Fanout Delay (ns) Site Resource ROUTE 46 3.173 OSC.OSC to R4C13B.CLK Clock -------- 3.173 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 65.687ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q Encoder2/Decrement_o_40 (from Clock +) Destination: FF Data in Counter2_i12 (to Clock +) Delay: 5.591ns (53.9% logic, 46.1% route), 9 logic levels. Constraint Details: 5.591ns physical path delay SLICE_39 to SLICE_36 meets 71.428ns delay constraint less 0.000ns skew and 0.150ns DIN_SET requirement (totaling 71.278ns) by 65.687ns Physical Path Details: Data path SLICE_39 to SLICE_36: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R7C15C.CLK to R7C15C.Q0 SLICE_39 (from Clock) ROUTE 1 1.705 R7C15C.Q0 to R7C10B.B0 Decrement2 C0TOFCO_DE --- 0.905 R7C10B.B0 to R7C10B.FCO SLICE_15 ROUTE 1 0.000 R7C10B.FCO to R7C10C.FCI n1182 FCITOFCO_D --- 0.146 R7C10C.FCI to R7C10C.FCO SLICE_14 ROUTE 1 0.000 R7C10C.FCO to R7C10D.FCI n1183 FCITOFCO_D --- 0.146 R7C10D.FCI to R7C10D.FCO SLICE_13 ROUTE 1 0.000 R7C10D.FCO to R7C11A.FCI n1184 FCITOFCO_D --- 0.146 R7C11A.FCI to R7C11A.FCO SLICE_12 ROUTE 1 0.000 R7C11A.FCO to R7C11B.FCI n1185 FCITOFCO_D --- 0.146 R7C11B.FCI to R7C11B.FCO SLICE_11 ROUTE 1 0.000 R7C11B.FCO to R7C11C.FCI n1186 FCITOFCO_D --- 0.146 R7C11C.FCI to R7C11C.FCO SLICE_2 ROUTE 1 0.000 R7C11C.FCO to R7C11D.FCI n1187 FCITOF0_DE --- 0.517 R7C11D.FCI to R7C11D.F0 SLICE_1 ROUTE 1 0.873 R7C11D.F0 to R8C11B.A1 n672 CTOF_DEL --- 0.452 R8C11B.A1 to R8C11B.F1 SLICE_36 ROUTE 1 0.000 R8C11B.F1 to R8C11B.DI1 Counter2_15_N_19_12 (to Clock) -------- 5.591 (53.9% logic, 46.1% route), 9 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_39: Name Fanout Delay (ns) Site Resource ROUTE 46 3.173 OSC.OSC to R7C15C.CLK Clock -------- 3.173 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_36: Name Fanout Delay (ns) Site Resource ROUTE 46 3.173 OSC.OSC to R8C11B.CLK Clock -------- 3.173 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 65.739ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q Encoder2/Increment_o_39 (from Clock +) Destination: FF Data in Counter2_i12 (to Clock +) Delay: 5.539ns (54.9% logic, 45.1% route), 10 logic levels. Constraint Details: 5.539ns physical path delay Encoder2/SLICE_51 to SLICE_36 meets 71.428ns delay constraint less 0.000ns skew and 0.150ns DIN_SET requirement (totaling 71.278ns) by 65.739ns Physical Path Details: Data path Encoder2/SLICE_51 to SLICE_36: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R7C15D.CLK to R7C15D.Q0 Encoder2/SLICE_51 (from Clock) ROUTE 17 1.626 R7C15D.Q0 to R7C10A.A1 Increment2 C1TOFCO_DE --- 0.786 R7C10A.A1 to R7C10A.FCO SLICE_16 ROUTE 1 0.000 R7C10A.FCO to R7C10B.FCI n1181 FCITOFCO_D --- 0.146 R7C10B.FCI to R7C10B.FCO SLICE_15 ROUTE 1 0.000 R7C10B.FCO to R7C10C.FCI n1182 FCITOFCO_D --- 0.146 R7C10C.FCI to R7C10C.FCO SLICE_14 ROUTE 1 0.000 R7C10C.FCO to R7C10D.FCI n1183 FCITOFCO_D --- 0.146 R7C10D.FCI to R7C10D.FCO SLICE_13 ROUTE 1 0.000 R7C10D.FCO to R7C11A.FCI n1184 FCITOFCO_D --- 0.146 R7C11A.FCI to R7C11A.FCO SLICE_12 ROUTE 1 0.000 R7C11A.FCO to R7C11B.FCI n1185 FCITOFCO_D --- 0.146 R7C11B.FCI to R7C11B.FCO SLICE_11 ROUTE 1 0.000 R7C11B.FCO to R7C11C.FCI n1186 FCITOFCO_D --- 0.146 R7C11C.FCI to R7C11C.FCO SLICE_2 ROUTE 1 0.000 R7C11C.FCO to R7C11D.FCI n1187 FCITOF0_DE --- 0.517 R7C11D.FCI to R7C11D.F0 SLICE_1 ROUTE 1 0.873 R7C11D.F0 to R8C11B.A1 n672 CTOF_DEL --- 0.452 R8C11B.A1 to R8C11B.F1 SLICE_36 ROUTE 1 0.000 R8C11B.F1 to R8C11B.DI1 Counter2_15_N_19_12 (to Clock) -------- 5.539 (54.9% logic, 45.1% route), 10 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to Encoder2/SLICE_51: Name Fanout Delay (ns) Site Resource ROUTE 46 3.173 OSC.OSC to R7C15D.CLK Clock -------- 3.173 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_36: Name Fanout Delay (ns) Site Resource ROUTE 46 3.173 OSC.OSC to R8C11B.CLK Clock -------- 3.173 (0.0% logic, 100.0% route), 0 logic levels. Report: 167.757MHz is the maximum frequency for this preference. Report Summary -------------- ---------------------------------------------------------------------------- Preference | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY NET "Clock" 14.000112 MHz ; | 14.000 MHz| 167.757 MHz| 4 | | | ---------------------------------------------------------------------------- All preferences were met. Clock Domains Analysis ------------------------ Found 1 clocks: Clock Domain: Clock Source: OSCH_inst.OSC Loads: 46 Covered under: FREQUENCY NET "Clock" 14.000112 MHz ; Timing summary (Setup): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 955 paths, 1 nets, and 569 connections (98.61% coverage) -------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 Mon Sep 04 21:30:27 2023 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Command line: trce -v 10 -gt -sethld -sp 5 -sphld m -o Enkoder_impl1.twr -gui -msgset C:/Lattice/Kurs14/promote.xml Enkoder_impl1.ncd Enkoder_impl1.prf Design file: enkoder_impl1.ncd Preference file: enkoder_impl1.prf Device,speed: LCMXO2-1200HC,m Report level: verbose report, limited to 10 items per preference -------------------------------------------------------------------------------- Preference Summary
  • FREQUENCY NET "Clock" 14.000112 MHz (0 errors)
  • 955 items scored, 0 timing errors detected. BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- Derating parameters ------------------- Temperature: 85 C Voltage: 3.300 V ================================================================================ Preference: FREQUENCY NET "Clock" 14.000112 MHz ; 955 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 0.322ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q Encoder1/SynchronizerA/R2_i1 (from Clock +) Destination: FF Data in Encoder1/EdgeDetector_inst/Previous_13 (to Clock +) Delay: 0.302ns (46.4% logic, 53.6% route), 1 logic levels. Constraint Details: 0.302ns physical path delay SLICE_54 to SLICE_54 meets -0.020ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.020ns) by 0.322ns Physical Path Details: Data path SLICE_54 to SLICE_54: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.140 R9C12A.CLK to R9C12A.Q1 SLICE_54 (from Clock) ROUTE 12 0.162 R9C12A.Q1 to R9C12A.M0 LED1_c_0 (to Clock) -------- 0.302 (46.4% logic, 53.6% route), 1 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_54: Name Fanout Delay (ns) Site Resource ROUTE 46 1.274 OSC.OSC to R9C12A.CLK Clock -------- 1.274 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_54: Name Fanout Delay (ns) Site Resource ROUTE 46 1.274 OSC.OSC to R9C12A.CLK Clock -------- 1.274 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.332ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q Encoder2/SynchronizerA/R2_i1 (from Clock +) Destination: FF Data in Encoder2/EdgeDetector_inst/Previous_13 (to Clock +) Delay: 0.312ns (44.9% logic, 55.1% route), 1 logic levels. Constraint Details: 0.312ns physical path delay SLICE_55 to SLICE_55 meets -0.020ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.020ns) by 0.332ns Physical Path Details: Data path SLICE_55 to SLICE_55: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.140 R7C12C.CLK to R7C12C.Q1 SLICE_55 (from Clock) ROUTE 12 0.172 R7C12C.Q1 to R7C12C.M0 LED2_c_0 (to Clock) -------- 0.312 (44.9% logic, 55.1% route), 1 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_55: Name Fanout Delay (ns) Site Resource ROUTE 46 1.274 OSC.OSC to R7C12C.CLK Clock -------- 1.274 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_55: Name Fanout Delay (ns) Site Resource ROUTE 46 1.274 OSC.OSC to R7C12C.CLK Clock -------- 1.274 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.397ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DisplayMultiplex_inst/StrobeGenerator0/Counter_i5 (from Clock +) Destination: FF Data in DisplayMultiplex_inst/StrobeGenerator0/Counter_i5 (to Clock +) Delay: 0.384ns (64.1% logic, 35.9% route), 2 logic levels. Constraint Details: 0.384ns physical path delay DisplayMultiplex_inst/StrobeGenerator0/SLICE_10 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_10 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.397ns Physical Path Details: Data path DisplayMultiplex_inst/StrobeGenerator0/SLICE_10 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_10: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.140 R4C12D.CLK to R4C12D.Q0 DisplayMultiplex_inst/StrobeGenerator0/SLICE_10 (from Clock) ROUTE 2 0.138 R4C12D.Q0 to R4C12D.A0 DisplayMultiplex_inst/StrobeGenerator0/Counter_5 CTOF_DEL --- 0.106 R4C12D.A0 to R4C12D.F0 DisplayMultiplex_inst/StrobeGenerator0/SLICE_10 ROUTE 1 0.000 R4C12D.F0 to R4C12D.DI0 DisplayMultiplex_inst/StrobeGenerator0/n14 (to Clock) -------- 0.384 (64.1% logic, 35.9% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to DisplayMultiplex_inst/StrobeGenerator0/SLICE_10: Name Fanout Delay (ns) Site Resource ROUTE 46 1.274 OSC.OSC to R4C12D.CLK Clock -------- 1.274 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to DisplayMultiplex_inst/StrobeGenerator0/SLICE_10: Name Fanout Delay (ns) Site Resource ROUTE 46 1.274 OSC.OSC to R4C12D.CLK Clock -------- 1.274 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.397ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DisplayMultiplex_inst/StrobeGenerator0/Counter_i9 (from Clock +) Destination: FF Data in DisplayMultiplex_inst/StrobeGenerator0/Counter_i9 (to Clock +) Delay: 0.384ns (64.1% logic, 35.9% route), 2 logic levels. Constraint Details: 0.384ns physical path delay DisplayMultiplex_inst/StrobeGenerator0/SLICE_7 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_7 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.397ns Physical Path Details: Data path DisplayMultiplex_inst/StrobeGenerator0/SLICE_7 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_7: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.140 R4C13B.CLK to R4C13B.Q0 DisplayMultiplex_inst/StrobeGenerator0/SLICE_7 (from Clock) ROUTE 2 0.138 R4C13B.Q0 to R4C13B.A0 DisplayMultiplex_inst/StrobeGenerator0/Counter_9 CTOF_DEL --- 0.106 R4C13B.A0 to R4C13B.F0 DisplayMultiplex_inst/StrobeGenerator0/SLICE_7 ROUTE 1 0.000 R4C13B.F0 to R4C13B.DI0 DisplayMultiplex_inst/StrobeGenerator0/n10 (to Clock) -------- 0.384 (64.1% logic, 35.9% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to DisplayMultiplex_inst/StrobeGenerator0/SLICE_7: Name Fanout Delay (ns) Site Resource ROUTE 46 1.274 OSC.OSC to R4C13B.CLK Clock -------- 1.274 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to DisplayMultiplex_inst/StrobeGenerator0/SLICE_7: Name Fanout Delay (ns) Site Resource ROUTE 46 1.274 OSC.OSC to R4C13B.CLK Clock -------- 1.274 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.397ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DisplayMultiplex_inst/StrobeGenerator0/Counter_i3 (from Clock +) Destination: FF Data in DisplayMultiplex_inst/StrobeGenerator0/Counter_i3 (to Clock +) Delay: 0.384ns (64.1% logic, 35.9% route), 2 logic levels. Constraint Details: 0.384ns physical path delay DisplayMultiplex_inst/StrobeGenerator0/SLICE_3 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_3 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.397ns Physical Path Details: Data path DisplayMultiplex_inst/StrobeGenerator0/SLICE_3 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_3: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.140 R4C12C.CLK to R4C12C.Q0 DisplayMultiplex_inst/StrobeGenerator0/SLICE_3 (from Clock) ROUTE 2 0.138 R4C12C.Q0 to R4C12C.A0 DisplayMultiplex_inst/StrobeGenerator0/Counter_3 CTOF_DEL --- 0.106 R4C12C.A0 to R4C12C.F0 DisplayMultiplex_inst/StrobeGenerator0/SLICE_3 ROUTE 1 0.000 R4C12C.F0 to R4C12C.DI0 DisplayMultiplex_inst/StrobeGenerator0/n16 (to Clock) -------- 0.384 (64.1% logic, 35.9% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to DisplayMultiplex_inst/StrobeGenerator0/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 46 1.274 OSC.OSC to R4C12C.CLK Clock -------- 1.274 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to DisplayMultiplex_inst/StrobeGenerator0/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 46 1.274 OSC.OSC to R4C12C.CLK Clock -------- 1.274 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.397ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DisplayMultiplex_inst/StrobeGenerator0/Counter_i6 (from Clock +) Destination: FF Data in DisplayMultiplex_inst/StrobeGenerator0/Counter_i6 (to Clock +) Delay: 0.384ns (64.1% logic, 35.9% route), 2 logic levels. Constraint Details: 0.384ns physical path delay DisplayMultiplex_inst/StrobeGenerator0/SLICE_10 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_10 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.397ns Physical Path Details: Data path DisplayMultiplex_inst/StrobeGenerator0/SLICE_10 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_10: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.140 R4C12D.CLK to R4C12D.Q1 DisplayMultiplex_inst/StrobeGenerator0/SLICE_10 (from Clock) ROUTE 2 0.138 R4C12D.Q1 to R4C12D.A1 DisplayMultiplex_inst/StrobeGenerator0/Counter_6 CTOF_DEL --- 0.106 R4C12D.A1 to R4C12D.F1 DisplayMultiplex_inst/StrobeGenerator0/SLICE_10 ROUTE 1 0.000 R4C12D.F1 to R4C12D.DI1 DisplayMultiplex_inst/StrobeGenerator0/n13 (to Clock) -------- 0.384 (64.1% logic, 35.9% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to DisplayMultiplex_inst/StrobeGenerator0/SLICE_10: Name Fanout Delay (ns) Site Resource ROUTE 46 1.274 OSC.OSC to R4C12D.CLK Clock -------- 1.274 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to DisplayMultiplex_inst/StrobeGenerator0/SLICE_10: Name Fanout Delay (ns) Site Resource ROUTE 46 1.274 OSC.OSC to R4C12D.CLK Clock -------- 1.274 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.397ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DisplayMultiplex_inst/StrobeGenerator0/Counter_i1 (from Clock +) Destination: FF Data in DisplayMultiplex_inst/StrobeGenerator0/Counter_i1 (to Clock +) Delay: 0.384ns (64.1% logic, 35.9% route), 2 logic levels. Constraint Details: 0.384ns physical path delay DisplayMultiplex_inst/StrobeGenerator0/SLICE_8 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_8 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.397ns Physical Path Details: Data path DisplayMultiplex_inst/StrobeGenerator0/SLICE_8 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_8: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.140 R4C12B.CLK to R4C12B.Q0 DisplayMultiplex_inst/StrobeGenerator0/SLICE_8 (from Clock) ROUTE 2 0.138 R4C12B.Q0 to R4C12B.A0 DisplayMultiplex_inst/StrobeGenerator0/Counter_1 CTOF_DEL --- 0.106 R4C12B.A0 to R4C12B.F0 DisplayMultiplex_inst/StrobeGenerator0/SLICE_8 ROUTE 1 0.000 R4C12B.F0 to R4C12B.DI0 DisplayMultiplex_inst/StrobeGenerator0/n18 (to Clock) -------- 0.384 (64.1% logic, 35.9% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to DisplayMultiplex_inst/StrobeGenerator0/SLICE_8: Name Fanout Delay (ns) Site Resource ROUTE 46 1.274 OSC.OSC to R4C12B.CLK Clock -------- 1.274 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to DisplayMultiplex_inst/StrobeGenerator0/SLICE_8: Name Fanout Delay (ns) Site Resource ROUTE 46 1.274 OSC.OSC to R4C12B.CLK Clock -------- 1.274 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.397ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DisplayMultiplex_inst/StrobeGenerator0/Counter_i0 (from Clock +) Destination: FF Data in DisplayMultiplex_inst/StrobeGenerator0/Counter_i0 (to Clock +) Delay: 0.384ns (64.1% logic, 35.9% route), 2 logic levels. Constraint Details: 0.384ns physical path delay DisplayMultiplex_inst/StrobeGenerator0/SLICE_5 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_5 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.397ns Physical Path Details: Data path DisplayMultiplex_inst/StrobeGenerator0/SLICE_5 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_5: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.140 R4C12A.CLK to R4C12A.Q1 DisplayMultiplex_inst/StrobeGenerator0/SLICE_5 (from Clock) ROUTE 2 0.138 R4C12A.Q1 to R4C12A.A1 DisplayMultiplex_inst/StrobeGenerator0/Counter_0 CTOF_DEL --- 0.106 R4C12A.A1 to R4C12A.F1 DisplayMultiplex_inst/StrobeGenerator0/SLICE_5 ROUTE 1 0.000 R4C12A.F1 to R4C12A.DI1 DisplayMultiplex_inst/StrobeGenerator0/n19 (to Clock) -------- 0.384 (64.1% logic, 35.9% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to DisplayMultiplex_inst/StrobeGenerator0/SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 46 1.274 OSC.OSC to R4C12A.CLK Clock -------- 1.274 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to DisplayMultiplex_inst/StrobeGenerator0/SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 46 1.274 OSC.OSC to R4C12A.CLK Clock -------- 1.274 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.397ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DisplayMultiplex_inst/StrobeGenerator0/Counter_i8 (from Clock +) Destination: FF Data in DisplayMultiplex_inst/StrobeGenerator0/Counter_i8 (to Clock +) Delay: 0.384ns (64.1% logic, 35.9% route), 2 logic levels. Constraint Details: 0.384ns physical path delay DisplayMultiplex_inst/StrobeGenerator0/SLICE_6 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_6 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.397ns Physical Path Details: Data path DisplayMultiplex_inst/StrobeGenerator0/SLICE_6 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_6: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.140 R4C13A.CLK to R4C13A.Q1 DisplayMultiplex_inst/StrobeGenerator0/SLICE_6 (from Clock) ROUTE 2 0.138 R4C13A.Q1 to R4C13A.A1 DisplayMultiplex_inst/StrobeGenerator0/Counter_8 CTOF_DEL --- 0.106 R4C13A.A1 to R4C13A.F1 DisplayMultiplex_inst/StrobeGenerator0/SLICE_6 ROUTE 1 0.000 R4C13A.F1 to R4C13A.DI1 DisplayMultiplex_inst/StrobeGenerator0/n11 (to Clock) -------- 0.384 (64.1% logic, 35.9% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to DisplayMultiplex_inst/StrobeGenerator0/SLICE_6: Name Fanout Delay (ns) Site Resource ROUTE 46 1.274 OSC.OSC to R4C13A.CLK Clock -------- 1.274 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to DisplayMultiplex_inst/StrobeGenerator0/SLICE_6: Name Fanout Delay (ns) Site Resource ROUTE 46 1.274 OSC.OSC to R4C13A.CLK Clock -------- 1.274 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.397ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DisplayMultiplex_inst/StrobeGenerator0/Counter_i7 (from Clock +) Destination: FF Data in DisplayMultiplex_inst/StrobeGenerator0/Counter_i7 (to Clock +) Delay: 0.384ns (64.1% logic, 35.9% route), 2 logic levels. Constraint Details: 0.384ns physical path delay DisplayMultiplex_inst/StrobeGenerator0/SLICE_6 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_6 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.397ns Physical Path Details: Data path DisplayMultiplex_inst/StrobeGenerator0/SLICE_6 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_6: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.140 R4C13A.CLK to R4C13A.Q0 DisplayMultiplex_inst/StrobeGenerator0/SLICE_6 (from Clock) ROUTE 2 0.138 R4C13A.Q0 to R4C13A.A0 DisplayMultiplex_inst/StrobeGenerator0/Counter_7 CTOF_DEL --- 0.106 R4C13A.A0 to R4C13A.F0 DisplayMultiplex_inst/StrobeGenerator0/SLICE_6 ROUTE 1 0.000 R4C13A.F0 to R4C13A.DI0 DisplayMultiplex_inst/StrobeGenerator0/n12 (to Clock) -------- 0.384 (64.1% logic, 35.9% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to DisplayMultiplex_inst/StrobeGenerator0/SLICE_6: Name Fanout Delay (ns) Site Resource ROUTE 46 1.274 OSC.OSC to R4C13A.CLK Clock -------- 1.274 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to DisplayMultiplex_inst/StrobeGenerator0/SLICE_6: Name Fanout Delay (ns) Site Resource ROUTE 46 1.274 OSC.OSC to R4C13A.CLK Clock -------- 1.274 (0.0% logic, 100.0% route), 0 logic levels. Report Summary -------------- ---------------------------------------------------------------------------- Preference(MIN Delays) | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY NET "Clock" 14.000112 MHz ; | 0.000 ns| 0.322 ns| 1 | | | ---------------------------------------------------------------------------- All preferences were met. Clock Domains Analysis ------------------------ Found 1 clocks: Clock Domain: Clock Source: OSCH_inst.OSC Loads: 46 Covered under: FREQUENCY NET "Clock" 14.000112 MHz ; Timing summary (Hold): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 955 paths, 1 nets, and 569 connections (98.61% coverage) Timing summary (Setup and Hold): --------------- Timing errors: 0 (setup), 0 (hold) Score: 0 (setup), 0 (hold) Cumulative negative slack: 0 (0+0) -------------------------------------------------------------------------------- --------------------------------------------------------------------------------