PAR: Place And Route Diamond (64-bit) 3.12.1.454.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
Thu Sep 21 13:25:16 2023

C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f Kurs15_impl1.p2t
Kurs15_impl1_map.ncd Kurs15_impl1.dir Kurs15_impl1.prf -gui -msgset
C:/Lattice/Kurs15/promote.xml


Preference file: Kurs15_impl1.prf.

Cost Table Summary
Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
----------   --------     -----        ------       -----------  -----------  ----         ------
5_1   *      0            65.367       0            0.212        0            03           Completed
* : Design saved.

Total (real) run time for 1-seed: 3 secs 

par done!

Note: user must run 'Trace' for timing closure signoff.

Lattice Place and Route Report for Design "Kurs15_impl1_map.ncd"
Thu Sep 21 13:25:16 2023


Best Par Run
PAR: Place And Route Diamond (64-bit) 3.12.1.454.
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/Lattice/Kurs15/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 Kurs15_impl1_map.ncd Kurs15_impl1.dir/5_1.ncd Kurs15_impl1.prf
Preference file: Kurs15_impl1.prf.
Placement level-cost: 5-1.
Routing Iterations: 6

Loading design for application par from file Kurs15_impl1_map.ncd.
Design name: top
NCD version: 3.3
Vendor:      LATTICE
Device:      LCMXO2-1200HC
Package:     TQFP100
Performance: 5
Loading device for application par from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status:                     Final          Version 1.44.
Performance Hardware Data Status:   Final          Version 34.4.
License checked out.


Ignore Preference Error(s):  True

Device utilization summary:

   PIO (prelim)   22+4(JTAG)/108     24% used
                  22+4(JTAG)/80      33% bonded

   SLICE             61/640           9% used

   GSR                1/1           100% used
   OSC                1/1           100% used
   EBR                1/7            14% used


INFO: Design contains EBR with ASYNC Reset Mode that has a limitation: The use of the EBR block asynchronous reset requires that certain timing be met between the clock and the reset within the memory block. See the device specific data sheet for additional details.
Number of Signals: 194
Number of Connections: 475

Pin Constraint Summary:
   22 out of 22 pins locked (100% locked).

The following 1 signal is selected to use the primary clock routing resources:
    Clock (driver: OSCH_inst, clk load #: 34)


No signal is selected as secondary clock.

Signal Reset_c is selected as Global Set/Reset.
Starting Placer Phase 0.
........
Finished Placer Phase 0.  REAL time: 0 secs 

Starting Placer Phase 1.
...................
Placer score = 19166.
Finished Placer Phase 1.  REAL time: 2 secs 

Starting Placer Phase 2.
.
Placer score =  19140
Finished Placer Phase 2.  REAL time: 2 secs 



Clock Report

Global Clock Resources:
  CLK_PIN    : 0 out of 8 (0%)
  PLL        : 0 out of 1 (0%)
  DCM        : 0 out of 2 (0%)
  DCC        : 0 out of 8 (0%)

Global Clocks:
  PRIMARY "Clock" from OSC on comp "OSCH_inst" on site "OSC", clk load = 34

  PRIMARY  : 1 out of 8 (12%)
  SECONDARY: 0 out of 8 (0%)

Edge Clocks:
  No edge clock selected.




I/O Usage Summary (final):
   22 + 4(JTAG) out of 108 (24.1%) PIO sites used.
   22 + 4(JTAG) out of 80 (32.5%) bonded PIO sites used.
   Number of PIO comps: 22; differential: 0.
   Number of Vref pins used: 0.

I/O Bank Usage Summary:
+----------+----------------+------------+-----------+
| I/O Bank | Usage          | Bank Vccio | Bank Vref |
+----------+----------------+------------+-----------+
| 0        | 0 / 19 (  0%)  | -          | -         |
| 1        | 6 / 21 ( 28%)  | 3.3V       | -         |
| 2        | 14 / 20 ( 70%) | 3.3V       | -         |
| 3        | 2 / 20 ( 10%)  | 3.3V       | -         |
+----------+----------------+------------+-----------+

Total placer CPU time: 1 secs 

Dumping design to file Kurs15_impl1.dir/5_1.ncd.

0 connections routed; 475 unrouted.
Starting router resource preassignment

Completed router resource preassignment. Real time: 2 secs 

Start NBR router at 13:25:18 09/21/23

*****************************************************************
Info: NBR allows conflicts(one node used by more than one signal)
      in the earlier iterations. In each iteration, it tries to  
      solve the conflicts while keeping the critical connections 
      routed as short as possible. The routing process is said to
      be completed when no conflicts exist and all connections   
      are routed.                                                
Note: NBR uses a different method to calculate timing slacks. The
      worst slack and total negative slack may not be the same as
      that in TRCE report. You should always run TRCE to verify  
      your design.                                               
*****************************************************************

Start NBR special constraint process at 13:25:18 09/21/23

Start NBR section for initial routing at 13:25:18 09/21/23
Level 4, iteration 1
13(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
Estimated worst slack/total negative slack<setup>: 65.367ns/0.000ns; real time: 2 secs 

Info: Initial congestion level at 75% usage is 0
Info: Initial congestion area  at 75% usage is 0 (0.00%)

Start NBR section for normal routing at 13:25:18 09/21/23
Level 4, iteration 1
8(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
Estimated worst slack/total negative slack<setup>: 65.367ns/0.000ns; real time: 2 secs 
Level 4, iteration 2
1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
Estimated worst slack/total negative slack<setup>: 65.367ns/0.000ns; real time: 2 secs 
Level 4, iteration 3
1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
Estimated worst slack/total negative slack<setup>: 65.367ns/0.000ns; real time: 2 secs 
Level 4, iteration 4
1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
Estimated worst slack/total negative slack<setup>: 65.367ns/0.000ns; real time: 2 secs 
Level 4, iteration 5
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
Estimated worst slack/total negative slack<setup>: 65.367ns/0.000ns; real time: 2 secs 

Start NBR section for setup/hold timing optimization with effort level 3 at 13:25:18 09/21/23

Start NBR section for re-routing at 13:25:19 09/21/23
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
Estimated worst slack/total negative slack<setup>: 65.367ns/0.000ns; real time: 3 secs 

Start NBR section for post-routing at 13:25:19 09/21/23

End NBR router with 0 unrouted connection

NBR Summary
-----------
  Number of unrouted connections : 0 (0.00%)
  Number of connections with timing violations : 0 (0.00%)
  Estimated worst slack<setup> : 65.367ns
  Timing score<setup> : 0
-----------
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.



Total CPU time 2 secs 
Total REAL time: 3 secs 
Completely routed.
End of route.  475 routed (100.00%); 0 unrouted.

Hold time timing score: 0, hold timing errors: 0

Timing score: 0 

Dumping design to file Kurs15_impl1.dir/5_1.ncd.


All signals are completely routed.


PAR_SUMMARY::Run status = Completed
PAR_SUMMARY::Number of unrouted conns = 0
PAR_SUMMARY::Worst  slack<setup/<ns>> = 65.367
PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
PAR_SUMMARY::Worst  slack<hold /<ns>> = 0.212
PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
PAR_SUMMARY::Number of errors = 0

Total CPU  time to completion: 2 secs 
Total REAL time to completion: 3 secs 

par done!

Note: user must run 'Trace' for timing closure signoff.

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.