Synthesis and Ngdbuild Report synthesis: version Diamond (64-bit) 3.12.1.454 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Thu Sep 21 13:25:14 2023 Command Line: synthesis -f Kurs15_impl1_lattice.synproj -gui -msgset C:/Lattice/Kurs15/promote.xml Synthesis options: The -a option is MachXO2. The -s option is 5. The -t option is TQFP100. The -d option is LCMXO2-1200HC. Using package TQFP100. Using performance grade 5. ########################################################## ### Lattice Family : MachXO2 ### Device : LCMXO2-1200HC ### Package : TQFP100 ### Speed : 5 ########################################################## INFO - synthesis: User-Selected Strategy Settings Optimization goal = Balanced Top-level module name = top. Target frequency = 200.000000 MHz. Maximum fanout = 1000. Timing path count = 3 BRAM utilization = 100.000000 % DSP usage = true DSP utilization = 100.000000 % fsm_encoding_style = auto resolve_mixed_drivers = 0 fix_gated_clocks = 1 Mux style = Auto Use Carry Chain = true carry_chain_length = 0 Loop Limit = 1950. Use IO Insertion = TRUE Use IO Reg = AUTO Resource Sharing = TRUE Propagate Constants = TRUE Remove Duplicate Registers = TRUE force_gsr = auto ROM style = auto RAM style = auto The -comp option is FALSE. The -syn option is FALSE. -p C:/Lattice/Kurs15 (searchpath added) -p C:/lscc/diamond/3.12/ispfpga/xo2c00/data (searchpath added) -p C:/Lattice/Kurs15/impl1 (searchpath added) -p C:/Lattice/Kurs15 (searchpath added) Verilog design file = C:/Lattice/Kurs15/impl1/source/top.v Verilog design file = C:/Lattice/Kurs15/impl1/source/display_multiplex.v Verilog design file = C:/Lattice/Kurs15/impl1/source/edge_detector.v Verilog design file = C:/Lattice/Kurs15/impl1/source/encoder.v Verilog design file = C:/Lattice/Kurs15/impl1/source/strobe_generator.v Verilog design file = C:/Lattice/Kurs15/impl1/source/synchronizer.v Verilog design file = C:/Lattice/Kurs15/impl1/source/decoder_7seg.v Verilog design file = C:/Lattice/Kurs15/impl1/source/ram.v NGD file = Kurs15_impl1.ngd -sdc option: SDC file input is C:/Lattice/Kurs15/impl1/source/timing.ldc. -lpf option: Output file option is ON. Hardtimer checking is enabled (default). The -dt option is not used. The -r option is OFF. [ Remove LOC Properties is OFF. ] Technology check ok... Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482 Compile design. Compile Design Begin Analyzing Verilog file c:/lattice/kurs15/impl1/source/top.v. VERI-1482 Analyzing Verilog file c:/lattice/kurs15/impl1/source/display_multiplex.v. VERI-1482 Analyzing Verilog file c:/lattice/kurs15/impl1/source/edge_detector.v. VERI-1482 Analyzing Verilog file c:/lattice/kurs15/impl1/source/encoder.v. VERI-1482 Analyzing Verilog file c:/lattice/kurs15/impl1/source/strobe_generator.v. VERI-1482 Analyzing Verilog file c:/lattice/kurs15/impl1/source/synchronizer.v. VERI-1482 Analyzing Verilog file c:/lattice/kurs15/impl1/source/decoder_7seg.v. VERI-1482 Analyzing Verilog file c:/lattice/kurs15/impl1/source/ram.v. VERI-1482 Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482 Top module name (Verilog): top INFO - synthesis: c:/lattice/kurs15/impl1/source/top.v(4): compiling module top. VERI-1018 INFO - synthesis: C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1793): compiling module OSCH(NOM_FREQ="14.00"). VERI-1018 INFO - synthesis: c:/lattice/kurs15/impl1/source/encoder.v(4): compiling module Encoder. VERI-1018 INFO - synthesis: c:/lattice/kurs15/impl1/source/synchronizer.v(4): compiling module Synchronizer(WIDTH=3). VERI-1018 INFO - synthesis: c:/lattice/kurs15/impl1/source/edge_detector.v(4): compiling module EdgeDetector. VERI-1018 INFO - synthesis: c:/lattice/kurs15/impl1/source/ram.v(4): compiling module RAM(ADDRESS_WIDTH=8). VERI-1018 INFO - synthesis: c:/lattice/kurs15/impl1/source/display_multiplex.v(4): compiling module DisplayMultiplex(CLOCK_HZ=14000000). VERI-1018 INFO - synthesis: c:/lattice/kurs15/impl1/source/strobe_generator.v(3): compiling module StrobeGenerator(CLOCK_HZ=14000000,PERIOD_US=1000). VERI-1018 INFO - synthesis: c:/lattice/kurs15/impl1/source/decoder_7seg.v(4): compiling module Decoder7seg. VERI-1018 Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00a/data/xo2alib.ngl'... Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'... Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... Loading device for application map from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga. Package Status: Final Version 1.44. Top-level module name = top. INFO - synthesis: Extracted state machine for register '\Encoder1/State' with one-hot encoding original encoding -> new encoding (one-hot encoding) 00 -> 0001 01 -> 0010 10 -> 0100 11 -> 1000 INFO - synthesis: Extracted state machine for register '\Encoder2/State' with one-hot encoding original encoding -> new encoding (one-hot encoding) 00 -> 0001 01 -> 0010 10 -> 0100 11 -> 1000 ######## Found 1 RTL RAMs in the design. ######## Mapping RTL RAM \RAM_inst/Memory to 1 EBR blocks in SINGLE_PORT Mode GSR instance connected to net Reset_c. Writing LPF file Kurs15_impl1.lpf. Results of NGD DRC are available in top_drc.log. Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00a/data/xo2alib.ngl'... Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'... Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... All blocks are expanded and NGD expansion is successful. Writing NGD file Kurs15_impl1.ngd. ################### Begin Area Report (top)###################### Number of register bits => 57 of 1520 (3 % ) CCU2D => 18 FD1P3AX => 3 FD1P3IX => 4 FD1S3AX => 34 FD1S3AY => 2 FD1S3IX => 4 FD1S3JX => 10 GSR => 1 IB => 6 LUT4 => 84 OB => 16 OSCH => 1 PFUMX => 6 SP8KC => 1 ################### End Area Report ################## ################### Begin BlackBox Report ###################### TSALL => 1 ################### End BlackBox Report ################## ################### Begin Clock Report ###################### Clock Nets Number of Clocks: 1 Net : Clock, loads : 58 Clock Enable Nets Number of Clock Enables: 3 Top 3 highest fanout Clock Enables: Net : Encoder1/Increment_o_N_63, loads : 2 Net : Encoder2/Increment_o_N_63, loads : 2 Highest fanout non-clock nets Top 10 highest fanout non-clock nets: Net : DisplayMultiplex_inst/TempData_3_N_110_2, loads : 27 Net : DisplayMultiplex_inst/TempData_3_N_110_3, loads : 20 Net : DisplayMultiplex_inst/TempData_3_N_110_4, loads : 19 Net : DisplayMultiplex_inst/StrobeGenerator0/Strobe_o_N_150, loads : 15 Net : Encoder1/AddressIncrement, loads : 9 Net : Encoder2/DataIncrement, loads : 9 Net : DisplayMultiplex_inst/TempData_0, loads : 7 Net : DisplayMultiplex_inst/TempData_1, loads : 7 Net : DisplayMultiplex_inst/n37, loads : 7 Net : DisplayMultiplex_inst/TempData_2, loads : 7 ################### End Clock Report ################## Timing Report Summary -------------- -------------------------------------------------------------------------------- Constraint | Constraint| Actual|Levels -------------------------------------------------------------------------------- | | | create_clock -period 71.428001 | | | -waveform { 0.000000 35.714001 } -name | | | Clock [ get_nets { Clock } ] | 14.000 MHz| 167.112 MHz| 4 | | | -------------------------------------------------------------------------------- All constraints were met. Peak Memory Usage: 56.293 MB -------------------------------------------------------------- Elapsed CPU time for LSE flow : 0.516 secs --------------------------------------------------------------