Place & Route TRACE Report

Loading design for application trce from file kurs15_impl1.ncd.
Design name: top
NCD version: 3.3
Vendor:      LATTICE
Device:      LCMXO2-1200HC
Package:     TQFP100
Performance: 5
Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status:                     Final          Version 1.44.
Performance Hardware Data Status:   Final          Version 34.4.
Setup and Hold Report

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Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
Thu Sep 21 13:25:19 2023

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
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Command line:    trce -v 10 -gt -sethld -sp 5 -sphld m -o Kurs15_impl1.twr -gui -msgset C:/Lattice/Kurs15/promote.xml Kurs15_impl1.ncd Kurs15_impl1.prf 
Design file:     kurs15_impl1.ncd
Preference file: kurs15_impl1.prf
Device,speed:    LCMXO2-1200HC,5
Report level:    verbose report, limited to 10 items per preference
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Preference Summary

  • FREQUENCY NET "Clock" 14.000112 MHz (0 errors)
  • 511 items scored, 0 timing errors detected. Report: 108.155MHz is the maximum frequency for this preference. BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- Derating parameters ------------------- Temperature: 85 C Voltage: 3.300 V ================================================================================ Preference: FREQUENCY NET "Clock" 14.000112 MHz ; 511 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 62.182ns The internal maximum frequency of the following component is 108.155 MHz Logical Details: Cell type Pin name Component name Destination: SP8KC CLKA RAM_inst/Memory0 Delay: 9.246ns -- based on Minimum Pulse Width Passed: The following path meets requirements by 65.367ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DisplayMultiplex_inst/StrobeGenerator0/Counter_i5 (from Clock +) Destination: FF Data in DisplayMultiplex_inst/StrobeGenerator0/Counter_i12 (to Clock +) FF DisplayMultiplex_inst/StrobeGenerator0/Counter_i11 Delay: 5.813ns (30.4% logic, 69.6% route), 4 logic levels. Constraint Details: 5.813ns physical path delay DisplayMultiplex_inst/StrobeGenerator0/SLICE_17 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_16 meets 71.428ns delay constraint less 0.000ns skew and 0.248ns LSR_SET requirement (totaling 71.180ns) by 65.367ns Physical Path Details: Data path DisplayMultiplex_inst/StrobeGenerator0/SLICE_17 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_16: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R3C14D.CLK to R3C14D.Q0 DisplayMultiplex_inst/StrobeGenerator0/SLICE_17 (from Clock) ROUTE 2 0.911 R3C14D.Q0 to R4C14A.B0 DisplayMultiplex_inst/StrobeGenerator0/Counter_5 CTOF_DEL --- 0.452 R4C14A.B0 to R4C14A.F0 SLICE_35 ROUTE 1 0.882 R4C14A.F0 to R4C15C.B1 DisplayMultiplex_inst/StrobeGenerator0/n18 CTOF_DEL --- 0.452 R4C15C.B1 to R4C15C.F1 DisplayMultiplex_inst/StrobeGenerator0/SLICE_55 ROUTE 1 0.882 R4C15C.F1 to R4C14C.B0 DisplayMultiplex_inst/StrobeGenerator0/n26 CTOF_DEL --- 0.452 R4C14C.B0 to R4C14C.F0 DisplayMultiplex_inst/StrobeGenerator0/SLICE_23 ROUTE 9 1.373 R4C14C.F0 to R3C15C.LSR DisplayMultiplex_inst/StrobeGenerator0/Strobe_o_N_150 (to Clock) -------- 5.813 (30.4% logic, 69.6% route), 4 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to DisplayMultiplex_inst/StrobeGenerator0/SLICE_17: Name Fanout Delay (ns) Site Resource ROUTE 34 3.173 OSC.OSC to R3C14D.CLK Clock -------- 3.173 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to DisplayMultiplex_inst/StrobeGenerator0/SLICE_16: Name Fanout Delay (ns) Site Resource ROUTE 34 3.173 OSC.OSC to R3C15C.CLK Clock -------- 3.173 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 65.367ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DisplayMultiplex_inst/StrobeGenerator0/Counter_i5 (from Clock +) Destination: FF Data in DisplayMultiplex_inst/StrobeGenerator0/Counter_i8 (to Clock +) FF DisplayMultiplex_inst/StrobeGenerator0/Counter_i7 Delay: 5.813ns (30.4% logic, 69.6% route), 4 logic levels. Constraint Details: 5.813ns physical path delay DisplayMultiplex_inst/StrobeGenerator0/SLICE_17 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_13 meets 71.428ns delay constraint less 0.000ns skew and 0.248ns LSR_SET requirement (totaling 71.180ns) by 65.367ns Physical Path Details: Data path DisplayMultiplex_inst/StrobeGenerator0/SLICE_17 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_13: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R3C14D.CLK to R3C14D.Q0 DisplayMultiplex_inst/StrobeGenerator0/SLICE_17 (from Clock) ROUTE 2 0.911 R3C14D.Q0 to R4C14A.B0 DisplayMultiplex_inst/StrobeGenerator0/Counter_5 CTOF_DEL --- 0.452 R4C14A.B0 to R4C14A.F0 SLICE_35 ROUTE 1 0.882 R4C14A.F0 to R4C15C.B1 DisplayMultiplex_inst/StrobeGenerator0/n18 CTOF_DEL --- 0.452 R4C15C.B1 to R4C15C.F1 DisplayMultiplex_inst/StrobeGenerator0/SLICE_55 ROUTE 1 0.882 R4C15C.F1 to R4C14C.B0 DisplayMultiplex_inst/StrobeGenerator0/n26 CTOF_DEL --- 0.452 R4C14C.B0 to R4C14C.F0 DisplayMultiplex_inst/StrobeGenerator0/SLICE_23 ROUTE 9 1.373 R4C14C.F0 to R3C15A.LSR DisplayMultiplex_inst/StrobeGenerator0/Strobe_o_N_150 (to Clock) -------- 5.813 (30.4% logic, 69.6% route), 4 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to DisplayMultiplex_inst/StrobeGenerator0/SLICE_17: Name Fanout Delay (ns) Site Resource ROUTE 34 3.173 OSC.OSC to R3C14D.CLK Clock -------- 3.173 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to DisplayMultiplex_inst/StrobeGenerator0/SLICE_13: Name Fanout Delay (ns) Site Resource ROUTE 34 3.173 OSC.OSC to R3C15A.CLK Clock -------- 3.173 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 65.367ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DisplayMultiplex_inst/StrobeGenerator0/Counter_i5 (from Clock +) Destination: FF Data in DisplayMultiplex_inst/StrobeGenerator0/Counter_i13 (to Clock +) Delay: 5.813ns (30.4% logic, 69.6% route), 4 logic levels. Constraint Details: 5.813ns physical path delay DisplayMultiplex_inst/StrobeGenerator0/SLICE_17 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_11 meets 71.428ns delay constraint less 0.000ns skew and 0.248ns LSR_SET requirement (totaling 71.180ns) by 65.367ns Physical Path Details: Data path DisplayMultiplex_inst/StrobeGenerator0/SLICE_17 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_11: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R3C14D.CLK to R3C14D.Q0 DisplayMultiplex_inst/StrobeGenerator0/SLICE_17 (from Clock) ROUTE 2 0.911 R3C14D.Q0 to R4C14A.B0 DisplayMultiplex_inst/StrobeGenerator0/Counter_5 CTOF_DEL --- 0.452 R4C14A.B0 to R4C14A.F0 SLICE_35 ROUTE 1 0.882 R4C14A.F0 to R4C15C.B1 DisplayMultiplex_inst/StrobeGenerator0/n18 CTOF_DEL --- 0.452 R4C15C.B1 to R4C15C.F1 DisplayMultiplex_inst/StrobeGenerator0/SLICE_55 ROUTE 1 0.882 R4C15C.F1 to R4C14C.B0 DisplayMultiplex_inst/StrobeGenerator0/n26 CTOF_DEL --- 0.452 R4C14C.B0 to R4C14C.F0 DisplayMultiplex_inst/StrobeGenerator0/SLICE_23 ROUTE 9 1.373 R4C14C.F0 to R3C15D.LSR DisplayMultiplex_inst/StrobeGenerator0/Strobe_o_N_150 (to Clock) -------- 5.813 (30.4% logic, 69.6% route), 4 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to DisplayMultiplex_inst/StrobeGenerator0/SLICE_17: Name Fanout Delay (ns) Site Resource ROUTE 34 3.173 OSC.OSC to R3C14D.CLK Clock -------- 3.173 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to DisplayMultiplex_inst/StrobeGenerator0/SLICE_11: Name Fanout Delay (ns) Site Resource ROUTE 34 3.173 OSC.OSC to R3C15D.CLK Clock -------- 3.173 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 65.367ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DisplayMultiplex_inst/StrobeGenerator0/Counter_i5 (from Clock +) Destination: FF Data in DisplayMultiplex_inst/StrobeGenerator0/Counter_i10 (to Clock +) FF DisplayMultiplex_inst/StrobeGenerator0/Counter_i9 Delay: 5.813ns (30.4% logic, 69.6% route), 4 logic levels. Constraint Details: 5.813ns physical path delay DisplayMultiplex_inst/StrobeGenerator0/SLICE_17 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_14 meets 71.428ns delay constraint less 0.000ns skew and 0.248ns LSR_SET requirement (totaling 71.180ns) by 65.367ns Physical Path Details: Data path DisplayMultiplex_inst/StrobeGenerator0/SLICE_17 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_14: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R3C14D.CLK to R3C14D.Q0 DisplayMultiplex_inst/StrobeGenerator0/SLICE_17 (from Clock) ROUTE 2 0.911 R3C14D.Q0 to R4C14A.B0 DisplayMultiplex_inst/StrobeGenerator0/Counter_5 CTOF_DEL --- 0.452 R4C14A.B0 to R4C14A.F0 SLICE_35 ROUTE 1 0.882 R4C14A.F0 to R4C15C.B1 DisplayMultiplex_inst/StrobeGenerator0/n18 CTOF_DEL --- 0.452 R4C15C.B1 to R4C15C.F1 DisplayMultiplex_inst/StrobeGenerator0/SLICE_55 ROUTE 1 0.882 R4C15C.F1 to R4C14C.B0 DisplayMultiplex_inst/StrobeGenerator0/n26 CTOF_DEL --- 0.452 R4C14C.B0 to R4C14C.F0 DisplayMultiplex_inst/StrobeGenerator0/SLICE_23 ROUTE 9 1.373 R4C14C.F0 to R3C15B.LSR DisplayMultiplex_inst/StrobeGenerator0/Strobe_o_N_150 (to Clock) -------- 5.813 (30.4% logic, 69.6% route), 4 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to DisplayMultiplex_inst/StrobeGenerator0/SLICE_17: Name Fanout Delay (ns) Site Resource ROUTE 34 3.173 OSC.OSC to R3C14D.CLK Clock -------- 3.173 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to DisplayMultiplex_inst/StrobeGenerator0/SLICE_14: Name Fanout Delay (ns) Site Resource ROUTE 34 3.173 OSC.OSC to R3C15B.CLK Clock -------- 3.173 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 65.398ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DisplayMultiplex_inst/StrobeGenerator0/Counter_i3 (from Clock +) Destination: FF Data in DisplayMultiplex_inst/StrobeGenerator0/Counter_i10 (to Clock +) FF DisplayMultiplex_inst/StrobeGenerator0/Counter_i9 Delay: 5.782ns (30.5% logic, 69.5% route), 4 logic levels. Constraint Details: 5.782ns physical path delay DisplayMultiplex_inst/StrobeGenerator0/SLICE_10 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_14 meets 71.428ns delay constraint less 0.000ns skew and 0.248ns LSR_SET requirement (totaling 71.180ns) by 65.398ns Physical Path Details: Data path DisplayMultiplex_inst/StrobeGenerator0/SLICE_10 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_14: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R3C14C.CLK to R3C14C.Q0 DisplayMultiplex_inst/StrobeGenerator0/SLICE_10 (from Clock) ROUTE 2 0.880 R3C14C.Q0 to R4C14A.A0 DisplayMultiplex_inst/StrobeGenerator0/Counter_3 CTOF_DEL --- 0.452 R4C14A.A0 to R4C14A.F0 SLICE_35 ROUTE 1 0.882 R4C14A.F0 to R4C15C.B1 DisplayMultiplex_inst/StrobeGenerator0/n18 CTOF_DEL --- 0.452 R4C15C.B1 to R4C15C.F1 DisplayMultiplex_inst/StrobeGenerator0/SLICE_55 ROUTE 1 0.882 R4C15C.F1 to R4C14C.B0 DisplayMultiplex_inst/StrobeGenerator0/n26 CTOF_DEL --- 0.452 R4C14C.B0 to R4C14C.F0 DisplayMultiplex_inst/StrobeGenerator0/SLICE_23 ROUTE 9 1.373 R4C14C.F0 to R3C15B.LSR DisplayMultiplex_inst/StrobeGenerator0/Strobe_o_N_150 (to Clock) -------- 5.782 (30.5% logic, 69.5% route), 4 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to DisplayMultiplex_inst/StrobeGenerator0/SLICE_10: Name Fanout Delay (ns) Site Resource ROUTE 34 3.173 OSC.OSC to R3C14C.CLK Clock -------- 3.173 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to DisplayMultiplex_inst/StrobeGenerator0/SLICE_14: Name Fanout Delay (ns) Site Resource ROUTE 34 3.173 OSC.OSC to R3C15B.CLK Clock -------- 3.173 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 65.398ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DisplayMultiplex_inst/StrobeGenerator0/Counter_i3 (from Clock +) Destination: FF Data in DisplayMultiplex_inst/StrobeGenerator0/Counter_i13 (to Clock +) Delay: 5.782ns (30.5% logic, 69.5% route), 4 logic levels. Constraint Details: 5.782ns physical path delay DisplayMultiplex_inst/StrobeGenerator0/SLICE_10 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_11 meets 71.428ns delay constraint less 0.000ns skew and 0.248ns LSR_SET requirement (totaling 71.180ns) by 65.398ns Physical Path Details: Data path DisplayMultiplex_inst/StrobeGenerator0/SLICE_10 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_11: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R3C14C.CLK to R3C14C.Q0 DisplayMultiplex_inst/StrobeGenerator0/SLICE_10 (from Clock) ROUTE 2 0.880 R3C14C.Q0 to R4C14A.A0 DisplayMultiplex_inst/StrobeGenerator0/Counter_3 CTOF_DEL --- 0.452 R4C14A.A0 to R4C14A.F0 SLICE_35 ROUTE 1 0.882 R4C14A.F0 to R4C15C.B1 DisplayMultiplex_inst/StrobeGenerator0/n18 CTOF_DEL --- 0.452 R4C15C.B1 to R4C15C.F1 DisplayMultiplex_inst/StrobeGenerator0/SLICE_55 ROUTE 1 0.882 R4C15C.F1 to R4C14C.B0 DisplayMultiplex_inst/StrobeGenerator0/n26 CTOF_DEL --- 0.452 R4C14C.B0 to R4C14C.F0 DisplayMultiplex_inst/StrobeGenerator0/SLICE_23 ROUTE 9 1.373 R4C14C.F0 to R3C15D.LSR DisplayMultiplex_inst/StrobeGenerator0/Strobe_o_N_150 (to Clock) -------- 5.782 (30.5% logic, 69.5% route), 4 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to DisplayMultiplex_inst/StrobeGenerator0/SLICE_10: Name Fanout Delay (ns) Site Resource ROUTE 34 3.173 OSC.OSC to R3C14C.CLK Clock -------- 3.173 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to DisplayMultiplex_inst/StrobeGenerator0/SLICE_11: Name Fanout Delay (ns) Site Resource ROUTE 34 3.173 OSC.OSC to R3C15D.CLK Clock -------- 3.173 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 65.398ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DisplayMultiplex_inst/StrobeGenerator0/Counter_i3 (from Clock +) Destination: FF Data in DisplayMultiplex_inst/StrobeGenerator0/Counter_i8 (to Clock +) FF DisplayMultiplex_inst/StrobeGenerator0/Counter_i7 Delay: 5.782ns (30.5% logic, 69.5% route), 4 logic levels. Constraint Details: 5.782ns physical path delay DisplayMultiplex_inst/StrobeGenerator0/SLICE_10 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_13 meets 71.428ns delay constraint less 0.000ns skew and 0.248ns LSR_SET requirement (totaling 71.180ns) by 65.398ns Physical Path Details: Data path DisplayMultiplex_inst/StrobeGenerator0/SLICE_10 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_13: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R3C14C.CLK to R3C14C.Q0 DisplayMultiplex_inst/StrobeGenerator0/SLICE_10 (from Clock) ROUTE 2 0.880 R3C14C.Q0 to R4C14A.A0 DisplayMultiplex_inst/StrobeGenerator0/Counter_3 CTOF_DEL --- 0.452 R4C14A.A0 to R4C14A.F0 SLICE_35 ROUTE 1 0.882 R4C14A.F0 to R4C15C.B1 DisplayMultiplex_inst/StrobeGenerator0/n18 CTOF_DEL --- 0.452 R4C15C.B1 to R4C15C.F1 DisplayMultiplex_inst/StrobeGenerator0/SLICE_55 ROUTE 1 0.882 R4C15C.F1 to R4C14C.B0 DisplayMultiplex_inst/StrobeGenerator0/n26 CTOF_DEL --- 0.452 R4C14C.B0 to R4C14C.F0 DisplayMultiplex_inst/StrobeGenerator0/SLICE_23 ROUTE 9 1.373 R4C14C.F0 to R3C15A.LSR DisplayMultiplex_inst/StrobeGenerator0/Strobe_o_N_150 (to Clock) -------- 5.782 (30.5% logic, 69.5% route), 4 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to DisplayMultiplex_inst/StrobeGenerator0/SLICE_10: Name Fanout Delay (ns) Site Resource ROUTE 34 3.173 OSC.OSC to R3C14C.CLK Clock -------- 3.173 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to DisplayMultiplex_inst/StrobeGenerator0/SLICE_13: Name Fanout Delay (ns) Site Resource ROUTE 34 3.173 OSC.OSC to R3C15A.CLK Clock -------- 3.173 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 65.398ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DisplayMultiplex_inst/StrobeGenerator0/Counter_i3 (from Clock +) Destination: FF Data in DisplayMultiplex_inst/StrobeGenerator0/Counter_i12 (to Clock +) FF DisplayMultiplex_inst/StrobeGenerator0/Counter_i11 Delay: 5.782ns (30.5% logic, 69.5% route), 4 logic levels. Constraint Details: 5.782ns physical path delay DisplayMultiplex_inst/StrobeGenerator0/SLICE_10 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_16 meets 71.428ns delay constraint less 0.000ns skew and 0.248ns LSR_SET requirement (totaling 71.180ns) by 65.398ns Physical Path Details: Data path DisplayMultiplex_inst/StrobeGenerator0/SLICE_10 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_16: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R3C14C.CLK to R3C14C.Q0 DisplayMultiplex_inst/StrobeGenerator0/SLICE_10 (from Clock) ROUTE 2 0.880 R3C14C.Q0 to R4C14A.A0 DisplayMultiplex_inst/StrobeGenerator0/Counter_3 CTOF_DEL --- 0.452 R4C14A.A0 to R4C14A.F0 SLICE_35 ROUTE 1 0.882 R4C14A.F0 to R4C15C.B1 DisplayMultiplex_inst/StrobeGenerator0/n18 CTOF_DEL --- 0.452 R4C15C.B1 to R4C15C.F1 DisplayMultiplex_inst/StrobeGenerator0/SLICE_55 ROUTE 1 0.882 R4C15C.F1 to R4C14C.B0 DisplayMultiplex_inst/StrobeGenerator0/n26 CTOF_DEL --- 0.452 R4C14C.B0 to R4C14C.F0 DisplayMultiplex_inst/StrobeGenerator0/SLICE_23 ROUTE 9 1.373 R4C14C.F0 to R3C15C.LSR DisplayMultiplex_inst/StrobeGenerator0/Strobe_o_N_150 (to Clock) -------- 5.782 (30.5% logic, 69.5% route), 4 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to DisplayMultiplex_inst/StrobeGenerator0/SLICE_10: Name Fanout Delay (ns) Site Resource ROUTE 34 3.173 OSC.OSC to R3C14C.CLK Clock -------- 3.173 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to DisplayMultiplex_inst/StrobeGenerator0/SLICE_16: Name Fanout Delay (ns) Site Resource ROUTE 34 3.173 OSC.OSC to R3C15C.CLK Clock -------- 3.173 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 65.746ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DisplayMultiplex_inst/StrobeGenerator0/Counter_i5 (from Clock +) Destination: FF Data in DisplayMultiplex_inst/StrobeGenerator0/Counter_i4 (to Clock +) FF DisplayMultiplex_inst/StrobeGenerator0/Counter_i3 Delay: 5.434ns (32.5% logic, 67.5% route), 4 logic levels. Constraint Details: 5.434ns physical path delay DisplayMultiplex_inst/StrobeGenerator0/SLICE_17 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_10 meets 71.428ns delay constraint less 0.000ns skew and 0.248ns LSR_SET requirement (totaling 71.180ns) by 65.746ns Physical Path Details: Data path DisplayMultiplex_inst/StrobeGenerator0/SLICE_17 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_10: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R3C14D.CLK to R3C14D.Q0 DisplayMultiplex_inst/StrobeGenerator0/SLICE_17 (from Clock) ROUTE 2 0.911 R3C14D.Q0 to R4C14A.B0 DisplayMultiplex_inst/StrobeGenerator0/Counter_5 CTOF_DEL --- 0.452 R4C14A.B0 to R4C14A.F0 SLICE_35 ROUTE 1 0.882 R4C14A.F0 to R4C15C.B1 DisplayMultiplex_inst/StrobeGenerator0/n18 CTOF_DEL --- 0.452 R4C15C.B1 to R4C15C.F1 DisplayMultiplex_inst/StrobeGenerator0/SLICE_55 ROUTE 1 0.882 R4C15C.F1 to R4C14C.B0 DisplayMultiplex_inst/StrobeGenerator0/n26 CTOF_DEL --- 0.452 R4C14C.B0 to R4C14C.F0 DisplayMultiplex_inst/StrobeGenerator0/SLICE_23 ROUTE 9 0.994 R4C14C.F0 to R3C14C.LSR DisplayMultiplex_inst/StrobeGenerator0/Strobe_o_N_150 (to Clock) -------- 5.434 (32.5% logic, 67.5% route), 4 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to DisplayMultiplex_inst/StrobeGenerator0/SLICE_17: Name Fanout Delay (ns) Site Resource ROUTE 34 3.173 OSC.OSC to R3C14D.CLK Clock -------- 3.173 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to DisplayMultiplex_inst/StrobeGenerator0/SLICE_10: Name Fanout Delay (ns) Site Resource ROUTE 34 3.173 OSC.OSC to R3C14C.CLK Clock -------- 3.173 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 65.746ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DisplayMultiplex_inst/StrobeGenerator0/Counter_i5 (from Clock +) Destination: FF Data in DisplayMultiplex_inst/StrobeGenerator0/Counter_i2 (to Clock +) FF DisplayMultiplex_inst/StrobeGenerator0/Counter_i1 Delay: 5.434ns (32.5% logic, 67.5% route), 4 logic levels. Constraint Details: 5.434ns physical path delay DisplayMultiplex_inst/StrobeGenerator0/SLICE_17 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_15 meets 71.428ns delay constraint less 0.000ns skew and 0.248ns LSR_SET requirement (totaling 71.180ns) by 65.746ns Physical Path Details: Data path DisplayMultiplex_inst/StrobeGenerator0/SLICE_17 to DisplayMultiplex_inst/StrobeGenerator0/SLICE_15: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R3C14D.CLK to R3C14D.Q0 DisplayMultiplex_inst/StrobeGenerator0/SLICE_17 (from Clock) ROUTE 2 0.911 R3C14D.Q0 to R4C14A.B0 DisplayMultiplex_inst/StrobeGenerator0/Counter_5 CTOF_DEL --- 0.452 R4C14A.B0 to R4C14A.F0 SLICE_35 ROUTE 1 0.882 R4C14A.F0 to R4C15C.B1 DisplayMultiplex_inst/StrobeGenerator0/n18 CTOF_DEL --- 0.452 R4C15C.B1 to R4C15C.F1 DisplayMultiplex_inst/StrobeGenerator0/SLICE_55 ROUTE 1 0.882 R4C15C.F1 to R4C14C.B0 DisplayMultiplex_inst/StrobeGenerator0/n26 CTOF_DEL --- 0.452 R4C14C.B0 to R4C14C.F0 DisplayMultiplex_inst/StrobeGenerator0/SLICE_23 ROUTE 9 0.994 R4C14C.F0 to R3C14B.LSR DisplayMultiplex_inst/StrobeGenerator0/Strobe_o_N_150 (to Clock) -------- 5.434 (32.5% logic, 67.5% route), 4 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to DisplayMultiplex_inst/StrobeGenerator0/SLICE_17: Name Fanout Delay (ns) Site Resource ROUTE 34 3.173 OSC.OSC to R3C14D.CLK Clock -------- 3.173 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to DisplayMultiplex_inst/StrobeGenerator0/SLICE_15: Name Fanout Delay (ns) Site Resource ROUTE 34 3.173 OSC.OSC to R3C14B.CLK Clock -------- 3.173 (0.0% logic, 100.0% route), 0 logic levels. Report: 108.155MHz is the maximum frequency for this preference. Report Summary -------------- ---------------------------------------------------------------------------- Preference | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY NET "Clock" 14.000112 MHz ; | 14.000 MHz| 108.155 MHz| 0 | | | ---------------------------------------------------------------------------- All preferences were met. Clock Domains Analysis ------------------------ Found 1 clocks: Clock Domain: Clock Source: OSCH_inst.OSC Loads: 34 Covered under: FREQUENCY NET "Clock" 14.000112 MHz ; Timing summary (Setup): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 511 paths, 1 nets, and 467 connections (98.32% coverage) -------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 Thu Sep 21 13:25:19 2023 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Command line: trce -v 10 -gt -sethld -sp 5 -sphld m -o Kurs15_impl1.twr -gui -msgset C:/Lattice/Kurs15/promote.xml Kurs15_impl1.ncd Kurs15_impl1.prf Design file: kurs15_impl1.ncd Preference file: kurs15_impl1.prf Device,speed: LCMXO2-1200HC,m Report level: verbose report, limited to 10 items per preference -------------------------------------------------------------------------------- Preference Summary
  • FREQUENCY NET "Clock" 14.000112 MHz (0 errors)
  • 511 items scored, 0 timing errors detected. BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- Derating parameters ------------------- Temperature: 85 C Voltage: 3.300 V ================================================================================ Preference: FREQUENCY NET "Clock" 14.000112 MHz ; 511 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 0.212ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DataToWrite_i1 (from Clock +) Destination: SP8KC Port RAM_inst/Memory0(ASIC) (to Clock +) Delay: 0.325ns (43.1% logic, 56.9% route), 1 logic levels. Constraint Details: 0.325ns physical path delay SLICE_3 to RAM_inst/Memory0 meets 0.056ns DATA_HLD and 0.000ns delay constraint less -0.057ns skew requirement (totaling 0.113ns) by 0.212ns Physical Path Details: Data path SLICE_3 to RAM_inst/Memory0: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.140 R4C11B.CLK to R4C11B.Q1 SLICE_3 (from Clock) ROUTE 4 0.185 R4C11B.Q1 to EBR_R6C10.DI1 DataToWrite_1 (to Clock) -------- 0.325 (43.1% logic, 56.9% route), 1 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 34 1.274 OSC.OSC to R4C11B.CLK Clock -------- 1.274 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to RAM_inst/Memory0: Name Fanout Delay (ns) Site Resource ROUTE 34 1.331 OSC.OSC to EBR_R6C10.CLK Clock -------- 1.331 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.247ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q Address_i1 (from Clock +) Destination: SP8KC Port RAM_inst/Memory0(ASIC) (to Clock +) Delay: 0.361ns (38.8% logic, 61.2% route), 1 logic levels. Constraint Details: 0.361ns physical path delay SLICE_8 to RAM_inst/Memory0 meets 0.057ns ADDR_HLD and 0.000ns delay constraint less -0.057ns skew requirement (totaling 0.114ns) by 0.247ns Physical Path Details: Data path SLICE_8 to RAM_inst/Memory0: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.140 R5C12B.CLK to R5C12B.Q1 SLICE_8 (from Clock) ROUTE 4 0.221 R5C12B.Q1 to EBR_R6C10.AD4 Address_1 (to Clock) -------- 0.361 (38.8% logic, 61.2% route), 1 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_8: Name Fanout Delay (ns) Site Resource ROUTE 34 1.274 OSC.OSC to R5C12B.CLK Clock -------- 1.274 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to RAM_inst/Memory0: Name Fanout Delay (ns) Site Resource ROUTE 34 1.331 OSC.OSC to EBR_R6C10.CLK Clock -------- 1.331 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.322ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q Encoder1/SynchronizerA/R2_i0 (from Clock +) Destination: FF Data in Encoder1/EdgeDetector_inst/Previous_13 (to Clock +) Delay: 0.302ns (46.4% logic, 53.6% route), 1 logic levels. Constraint Details: 0.302ns physical path delay SLICE_35 to SLICE_35 meets -0.020ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.020ns) by 0.322ns Physical Path Details: Data path SLICE_35 to SLICE_35: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.140 R4C14A.CLK to R4C14A.Q1 SLICE_35 (from Clock) ROUTE 2 0.162 R4C14A.Q1 to R4C14A.M0 ButtonState_o (to Clock) -------- 0.302 (46.4% logic, 53.6% route), 1 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_35: Name Fanout Delay (ns) Site Resource ROUTE 34 1.274 OSC.OSC to R4C14A.CLK Clock -------- 1.274 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_35: Name Fanout Delay (ns) Site Resource ROUTE 34 1.274 OSC.OSC to R4C14A.CLK Clock -------- 1.274 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.323ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DataToWrite_i4 (from Clock +) Destination: SP8KC Port RAM_inst/Memory0(ASIC) (to Clock +) Delay: 0.436ns (32.1% logic, 67.9% route), 1 logic levels. Constraint Details: 0.436ns physical path delay SLICE_1 to RAM_inst/Memory0 meets 0.056ns DATA_HLD and 0.000ns delay constraint less -0.057ns skew requirement (totaling 0.113ns) by 0.323ns Physical Path Details: Data path SLICE_1 to RAM_inst/Memory0: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.140 R4C11D.CLK to R4C11D.Q0 SLICE_1 (from Clock) ROUTE 4 0.296 R4C11D.Q0 to EBR_R6C10.DI4 DataToWrite_4 (to Clock) -------- 0.436 (32.1% logic, 67.9% route), 1 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 34 1.274 OSC.OSC to R4C11D.CLK Clock -------- 1.274 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to RAM_inst/Memory0: Name Fanout Delay (ns) Site Resource ROUTE 34 1.331 OSC.OSC to EBR_R6C10.CLK Clock -------- 1.331 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.327ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DataToWrite_i2 (from Clock +) Destination: SP8KC Port RAM_inst/Memory0(ASIC) (to Clock +) Delay: 0.440ns (31.8% logic, 68.2% route), 1 logic levels. Constraint Details: 0.440ns physical path delay SLICE_2 to RAM_inst/Memory0 meets 0.056ns DATA_HLD and 0.000ns delay constraint less -0.057ns skew requirement (totaling 0.113ns) by 0.327ns Physical Path Details: Data path SLICE_2 to RAM_inst/Memory0: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.140 R4C11C.CLK to R4C11C.Q0 SLICE_2 (from Clock) ROUTE 4 0.300 R4C11C.Q0 to EBR_R6C10.DI2 DataToWrite_2 (to Clock) -------- 0.440 (31.8% logic, 68.2% route), 1 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 34 1.274 OSC.OSC to R4C11C.CLK Clock -------- 1.274 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to RAM_inst/Memory0: Name Fanout Delay (ns) Site Resource ROUTE 34 1.331 OSC.OSC to EBR_R6C10.CLK Clock -------- 1.331 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.329ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DataToWrite_i6 (from Clock +) Destination: SP8KC Port RAM_inst/Memory0(ASIC) (to Clock +) Delay: 0.442ns (31.7% logic, 68.3% route), 1 logic levels. Constraint Details: 0.442ns physical path delay SLICE_0 to RAM_inst/Memory0 meets 0.056ns DATA_HLD and 0.000ns delay constraint less -0.057ns skew requirement (totaling 0.113ns) by 0.329ns Physical Path Details: Data path SLICE_0 to RAM_inst/Memory0: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.140 R4C12A.CLK to R4C12A.Q0 SLICE_0 (from Clock) ROUTE 4 0.302 R4C12A.Q0 to EBR_R6C10.DI6 DataToWrite_6 (to Clock) -------- 0.442 (31.7% logic, 68.3% route), 1 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_0: Name Fanout Delay (ns) Site Resource ROUTE 34 1.274 OSC.OSC to R4C12A.CLK Clock -------- 1.274 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to RAM_inst/Memory0: Name Fanout Delay (ns) Site Resource ROUTE 34 1.331 OSC.OSC to EBR_R6C10.CLK Clock -------- 1.331 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.332ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DataToWrite_i7 (from Clock +) Destination: SP8KC Port RAM_inst/Memory0(ASIC) (to Clock +) Delay: 0.445ns (31.5% logic, 68.5% route), 1 logic levels. Constraint Details: 0.445ns physical path delay SLICE_0 to RAM_inst/Memory0 meets 0.056ns DATA_HLD and 0.000ns delay constraint less -0.057ns skew requirement (totaling 0.113ns) by 0.332ns Physical Path Details: Data path SLICE_0 to RAM_inst/Memory0: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.140 R4C12A.CLK to R4C12A.Q1 SLICE_0 (from Clock) ROUTE 4 0.305 R4C12A.Q1 to EBR_R6C10.DI7 DataToWrite_7 (to Clock) -------- 0.445 (31.5% logic, 68.5% route), 1 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_0: Name Fanout Delay (ns) Site Resource ROUTE 34 1.274 OSC.OSC to R4C12A.CLK Clock -------- 1.274 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to RAM_inst/Memory0: Name Fanout Delay (ns) Site Resource ROUTE 34 1.331 OSC.OSC to EBR_R6C10.CLK Clock -------- 1.331 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.362ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q Encoder1/State_FSM_i3 (from Clock +) Destination: FF Data in Encoder1/Decrement_o_40 (to Clock +) Delay: 0.303ns (46.2% logic, 53.8% route), 1 logic levels. Constraint Details: 0.303ns physical path delay Encoder1/SLICE_36 to SLICE_18 meets -0.059ns LSR_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.059ns) by 0.362ns Physical Path Details: Data path Encoder1/SLICE_36 to SLICE_18: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.140 R5C11B.CLK to R5C11B.Q0 Encoder1/SLICE_36 (from Clock) ROUTE 6 0.163 R5C11B.Q0 to R5C11A.LSR n183 (to Clock) -------- 0.303 (46.2% logic, 53.8% route), 1 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to Encoder1/SLICE_36: Name Fanout Delay (ns) Site Resource ROUTE 34 1.274 OSC.OSC to R5C11B.CLK Clock -------- 1.274 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_18: Name Fanout Delay (ns) Site Resource ROUTE 34 1.274 OSC.OSC to R5C11A.CLK Clock -------- 1.274 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.362ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q Encoder1/State_FSM_i3 (from Clock +) Destination: FF Data in Encoder1/Increment_o_39 (to Clock +) Delay: 0.303ns (46.2% logic, 53.8% route), 1 logic levels. Constraint Details: 0.303ns physical path delay Encoder1/SLICE_36 to SLICE_19 meets -0.059ns LSR_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.059ns) by 0.362ns Physical Path Details: Data path Encoder1/SLICE_36 to SLICE_19: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.140 R5C11B.CLK to R5C11B.Q0 Encoder1/SLICE_36 (from Clock) ROUTE 6 0.163 R5C11B.Q0 to R5C11C.LSR n183 (to Clock) -------- 0.303 (46.2% logic, 53.8% route), 1 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to Encoder1/SLICE_36: Name Fanout Delay (ns) Site Resource ROUTE 34 1.274 OSC.OSC to R5C11B.CLK Clock -------- 1.274 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_19: Name Fanout Delay (ns) Site Resource ROUTE 34 1.274 OSC.OSC to R5C11C.CLK Clock -------- 1.274 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.368ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q Address_i2 (from Clock +) Destination: SP8KC Port RAM_inst/Memory0(ASIC) (to Clock +) Delay: 0.482ns (29.0% logic, 71.0% route), 1 logic levels. Constraint Details: 0.482ns physical path delay SLICE_7 to RAM_inst/Memory0 meets 0.057ns ADDR_HLD and 0.000ns delay constraint less -0.057ns skew requirement (totaling 0.114ns) by 0.368ns Physical Path Details: Data path SLICE_7 to RAM_inst/Memory0: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.140 R5C12C.CLK to R5C12C.Q0 SLICE_7 (from Clock) ROUTE 4 0.342 R5C12C.Q0 to EBR_R6C10.AD5 Address_2 (to Clock) -------- 0.482 (29.0% logic, 71.0% route), 1 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_7: Name Fanout Delay (ns) Site Resource ROUTE 34 1.274 OSC.OSC to R5C12C.CLK Clock -------- 1.274 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to RAM_inst/Memory0: Name Fanout Delay (ns) Site Resource ROUTE 34 1.331 OSC.OSC to EBR_R6C10.CLK Clock -------- 1.331 (0.0% logic, 100.0% route), 0 logic levels. Report Summary -------------- ---------------------------------------------------------------------------- Preference(MIN Delays) | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY NET "Clock" 14.000112 MHz ; | 0.000 ns| 0.212 ns| 1 | | | ---------------------------------------------------------------------------- All preferences were met. Clock Domains Analysis ------------------------ Found 1 clocks: Clock Domain: Clock Source: OSCH_inst.OSC Loads: 34 Covered under: FREQUENCY NET "Clock" 14.000112 MHz ; Timing summary (Hold): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 511 paths, 1 nets, and 467 connections (98.32% coverage) Timing summary (Setup and Hold): --------------- Timing errors: 0 (setup), 0 (hold) Score: 0 (setup), 0 (hold) Cumulative negative slack: 0 (0+0) -------------------------------------------------------------------------------- --------------------------------------------------------------------------------