Lattice Synthesis Timing Report -------------------------------------------------------------------------------- Lattice Synthesis Timing Report, Version Thu Sep 21 13:25:15 2023 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Design: top Constraint file: top_temp_lse.sdc Report level: verbose report, limited to 3 items per constraint -------------------------------------------------------------------------------- ================================================================================ Constraint: create_clock -period 71.428001 -waveform { 0.000000 35.714001 } -name Clock [ get_nets { Clock } ] 588 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 65.444ns Logical Details: Cell type Pin type Cell name (clock net +/-) Source: FD1S3JX CK \DisplayMultiplex_inst/StrobeGenerator0/Counter_i0 (from Clock +) Destination: FD1S3JX PD \DisplayMultiplex_inst/StrobeGenerator0/Counter_i0 (to Clock +) Delay: 5.838ns (29.9% logic, 70.1% route), 4 logic levels. Constraint Details: 5.838ns data_path \DisplayMultiplex_inst/StrobeGenerator0/Counter_i0 to \DisplayMultiplex_inst/StrobeGenerator0/Counter_i0 meets 71.428ns delay constraint less 0.146ns L_S requirement (totaling 71.282ns) by 65.444ns Path Details: \DisplayMultiplex_inst/StrobeGenerator0/Counter_i0 to \DisplayMultiplex_inst/StrobeGenerator0/Counter_i0 Name Fanout Delay (ns) Pins Resource(Cell.Net) L_CO --- 0.403 CK to Q \DisplayMultiplex_inst/StrobeGenerator0/Counter_i0 (from Clock) Route 2 e 1.002 \DisplayMultiplex_inst/StrobeGenerator0/Counter[0] LUT4 --- 0.448 A to Z \DisplayMultiplex_inst/StrobeGenerator0/i10_4_lut Route 1 e 0.788 \DisplayMultiplex_inst/StrobeGenerator0/n24 LUT4 --- 0.448 B to Z \DisplayMultiplex_inst/StrobeGenerator0/i12_4_lut Route 1 e 0.788 \DisplayMultiplex_inst/StrobeGenerator0/n26 LUT4 --- 0.448 B to Z \DisplayMultiplex_inst/StrobeGenerator0/i845_4_lut Route 15 e 1.513 \DisplayMultiplex_inst/StrobeGenerator0/Strobe_o_N_150 -------- 5.838 (29.9% logic, 70.1% route), 4 logic levels. Passed: The following path meets requirements by 65.444ns Logical Details: Cell type Pin type Cell name (clock net +/-) Source: FD1S3JX CK \DisplayMultiplex_inst/StrobeGenerator0/Counter_i0 (from Clock +) Destination: FD1S3AX D \DisplayMultiplex_inst/StrobeGenerator0/Strobe_o_15 (to Clock +) Delay: 5.838ns (29.9% logic, 70.1% route), 4 logic levels. Constraint Details: 5.838ns data_path \DisplayMultiplex_inst/StrobeGenerator0/Counter_i0 to \DisplayMultiplex_inst/StrobeGenerator0/Strobe_o_15 meets 71.428ns delay constraint less 0.146ns L_S requirement (totaling 71.282ns) by 65.444ns Path Details: \DisplayMultiplex_inst/StrobeGenerator0/Counter_i0 to \DisplayMultiplex_inst/StrobeGenerator0/Strobe_o_15 Name Fanout Delay (ns) Pins Resource(Cell.Net) L_CO --- 0.403 CK to Q \DisplayMultiplex_inst/StrobeGenerator0/Counter_i0 (from Clock) Route 2 e 1.002 \DisplayMultiplex_inst/StrobeGenerator0/Counter[0] LUT4 --- 0.448 A to Z \DisplayMultiplex_inst/StrobeGenerator0/i10_4_lut Route 1 e 0.788 \DisplayMultiplex_inst/StrobeGenerator0/n24 LUT4 --- 0.448 B to Z \DisplayMultiplex_inst/StrobeGenerator0/i12_4_lut Route 1 e 0.788 \DisplayMultiplex_inst/StrobeGenerator0/n26 LUT4 --- 0.448 B to Z \DisplayMultiplex_inst/StrobeGenerator0/i845_4_lut Route 15 e 1.513 \DisplayMultiplex_inst/StrobeGenerator0/Strobe_o_N_150 -------- 5.838 (29.9% logic, 70.1% route), 4 logic levels. Passed: The following path meets requirements by 65.444ns Logical Details: Cell type Pin type Cell name (clock net +/-) Source: FD1S3JX CK \DisplayMultiplex_inst/StrobeGenerator0/Counter_i0 (from Clock +) Destination: FD1S3JX PD \DisplayMultiplex_inst/StrobeGenerator0/Counter_i13 (to Clock +) Delay: 5.838ns (29.9% logic, 70.1% route), 4 logic levels. Constraint Details: 5.838ns data_path \DisplayMultiplex_inst/StrobeGenerator0/Counter_i0 to \DisplayMultiplex_inst/StrobeGenerator0/Counter_i13 meets 71.428ns delay constraint less 0.146ns L_S requirement (totaling 71.282ns) by 65.444ns Path Details: \DisplayMultiplex_inst/StrobeGenerator0/Counter_i0 to \DisplayMultiplex_inst/StrobeGenerator0/Counter_i13 Name Fanout Delay (ns) Pins Resource(Cell.Net) L_CO --- 0.403 CK to Q \DisplayMultiplex_inst/StrobeGenerator0/Counter_i0 (from Clock) Route 2 e 1.002 \DisplayMultiplex_inst/StrobeGenerator0/Counter[0] LUT4 --- 0.448 A to Z \DisplayMultiplex_inst/StrobeGenerator0/i10_4_lut Route 1 e 0.788 \DisplayMultiplex_inst/StrobeGenerator0/n24 LUT4 --- 0.448 B to Z \DisplayMultiplex_inst/StrobeGenerator0/i12_4_lut Route 1 e 0.788 \DisplayMultiplex_inst/StrobeGenerator0/n26 LUT4 --- 0.448 B to Z \DisplayMultiplex_inst/StrobeGenerator0/i845_4_lut Route 15 e 1.513 \DisplayMultiplex_inst/StrobeGenerator0/Strobe_o_N_150 -------- 5.838 (29.9% logic, 70.1% route), 4 logic levels. Report: 5.984 ns is the maximum delay for this constraint. Timing Report Summary -------------- -------------------------------------------------------------------------------- Constraint | Constraint| Actual|Levels -------------------------------------------------------------------------------- | | | create_clock -period 71.428001 | | | -waveform { 0.000000 35.714001 } -name | | | Clock [ get_nets { Clock } ] | 71.428 ns| 5.984 ns| 4 | | | -------------------------------------------------------------------------------- All constraints were met. Timing summary: --------------- Timing errors: 0 Score: 0 Constraints cover 618 paths, 136 nets, and 317 connections (61.1% coverage) Peak memory: 59015168 bytes, TRCE: 0 bytes, DLYMAN: 0 bytes CPU_TIME_REPORT: 0 secs