pn230905155245 #Start recording tcl command: 9/5/2023 15:05:52 #Project Location: C:/Lattice/Kurs15; Project name: Kurs15 prj_project new -name "Kurs15" -impl "impl1" -dev LCMXO2-1200HC-5TG100C -synthesis "lse" file copy -force -- "C:/Lattice/Kurs14/impl1/source/top.v" "C:/Lattice/Kurs14/impl1/source/display_multiplex.v" "C:/Lattice/Kurs14/impl1/source/edge_detector.v" "C:/Lattice/Kurs14/impl1/source/encoder.v" "C:/Lattice/Kurs14/impl1/source/strobe_generator.v" "C:/Lattice/Kurs15/impl1/source" file copy -force -- "C:/Lattice/Kurs14/impl1/source/synchronizer.v" "C:/Lattice/Kurs15/impl1/source" prj_src add "C:/Lattice/Kurs15/impl1/source/top.v" "C:/Lattice/Kurs15/impl1/source/display_multiplex.v" "C:/Lattice/Kurs15/impl1/source/edge_detector.v" "C:/Lattice/Kurs15/impl1/source/encoder.v" "C:/Lattice/Kurs15/impl1/source/strobe_generator.v" "C:/Lattice/Kurs15/impl1/source/synchronizer.v" prj_project save prj_run Synthesis -impl impl1 file copy -force -- "C:/Lattice/Kurs14/impl1/source/decoder_7seg.v" "C:/Lattice/Kurs15/impl1/source" prj_src add "C:/Lattice/Kurs15/impl1/source/decoder_7seg.v" prj_run Synthesis -impl impl1 file copy -force -- "C:/Lattice/Kurs14/Enkoder.lpf" "C:/Lattice/Kurs15/impl1/source" prj_src add -exclude "C:/Lattice/Kurs15/impl1/source/Enkoder.lpf" prj_src remove "C:/Lattice/Kurs15/impl1/source/Enkoder.lpf" prj_src add -exclude "C:/Lattice/Kurs15/impl1/source/constraints.lpf" prj_src enable "C:/Lattice/Kurs15/impl1/source/constraints.lpf" prj_src remove "C:/Lattice/Kurs15/Kurs15.lpf" prj_src add -exclude "C:/Lattice/Kurs15/impl1/source/timing.ldc" prj_src enable "C:/Lattice/Kurs15/impl1/source/timing.ldc" prj_run Synthesis -impl impl1 prj_run Synthesis -impl impl1 prj_run Synthesis -impl impl1 prj_run Synthesis -impl impl1 -task Lattice_Synthesis -forceOne prj_run Map -impl impl1 prj_run Synthesis -impl impl1 -forceOne prj_run Synthesis -impl impl1 prj_run Synthesis -impl impl1 -forceOne prj_run Synthesis -impl impl1 prj_run Map -impl impl1 prj_run PAR -impl impl1 prj_run Export -impl impl1 -task Bitgen prj_run Synthesis -impl impl1 prj_run Map -impl impl1 prj_run PAR -impl impl1 prj_src add "C:/verilog/ram/ram.v" prj_run Synthesis -impl impl1 prj_run Map -impl impl1 prj_run Synthesis -impl impl1 prj_run Map -impl impl1 prj_run Map -impl impl1 #Stop recording: 9/5/2023 15:52:45 pn230919200057 #Start recording tcl command: 9/19/2023 19:40:42 #Project Location: C:/Lattice/Kurs15; Project name: Kurs15 prj_project open "C:/Lattice/Kurs15/Kurs15.ldf" prj_src remove "C:/verilog/ram/ram.v" prj_src add "C:/Lattice/Kurs15/impl1/source/ram.v" prj_run Synthesis -impl impl1 prj_run Map -impl impl1 prj_run PAR -impl impl1 #Stop recording: 9/19/2023 20:00:57