Lattice Synthesis Timing Report
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Lattice Synthesis Timing Report, Version
Thu Oct 24 20:15:59 2024
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Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2023 Lattice Semiconductor Corporation, All rights reserved.
Report Information
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Design: top
Constraint file:
Report level: verbose report, limited to 3 items per constraint
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Constraint: create_clock -period 5.000000 -name clk0 [get_nets Clock_c]
1233 items scored, 887 timing errors detected.
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Error: The following path violates requirements by 4.773ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FD1S3IX CK \VGA_inst/HCounter_83__i4 (from Clock_c +)
Destination: FD1P3IX CD \VGA_inst/VDivider_86__i1 (to Clock_c +)
Delay: 9.627ns (27.5% logic, 72.5% route), 6 logic levels.
Constraint Details:
9.627ns data_path \VGA_inst/HCounter_83__i4 to \VGA_inst/VDivider_86__i1 violates
5.000ns delay constraint less
0.146ns L_S requirement (totaling 4.854ns) by 4.773ns
Path Details: \VGA_inst/HCounter_83__i4 to \VGA_inst/VDivider_86__i1
Name Fanout Delay (ns) Pins Resource(Cell.Net)
L_CO --- 0.403 CK to Q \VGA_inst/HCounter_83__i4 (from Clock_c)
Route 7 e 1.303 \VGA_inst/HCounter[4]
LUT4 --- 0.448 A to Z \VGA_inst/i1_2_lut_adj_18
Route 1 e 0.788 \VGA_inst/n4_adj_232
LUT4 --- 0.448 D to Z \VGA_inst/i1_4_lut_adj_17
Route 1 e 0.788 \VGA_inst/n987
LUT4 --- 0.448 B to Z \VGA_inst/i4_4_lut_adj_15
Route 23 e 1.533 \VGA_inst/Clock_c_enable_50
LUT4 --- 0.448 D to Z \VGA_inst/i1_2_lut_rep_9_4_lut
Route 18 e 1.521 \VGA_inst/Clock_c_enable_52
LUT4 --- 0.448 A to Z \VGA_inst/i363_4_lut
Route 3 e 1.051 \VGA_inst/n454
--------
9.627 (27.5% logic, 72.5% route), 6 logic levels.
Error: The following path violates requirements by 4.773ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FD1S3IX CK \VGA_inst/HCounter_83__i4 (from Clock_c +)
Destination: FD1P3IX CD \VGA_inst/VDivider_86__i2 (to Clock_c +)
Delay: 9.627ns (27.5% logic, 72.5% route), 6 logic levels.
Constraint Details:
9.627ns data_path \VGA_inst/HCounter_83__i4 to \VGA_inst/VDivider_86__i2 violates
5.000ns delay constraint less
0.146ns L_S requirement (totaling 4.854ns) by 4.773ns
Path Details: \VGA_inst/HCounter_83__i4 to \VGA_inst/VDivider_86__i2
Name Fanout Delay (ns) Pins Resource(Cell.Net)
L_CO --- 0.403 CK to Q \VGA_inst/HCounter_83__i4 (from Clock_c)
Route 7 e 1.303 \VGA_inst/HCounter[4]
LUT4 --- 0.448 A to Z \VGA_inst/i1_2_lut_adj_18
Route 1 e 0.788 \VGA_inst/n4_adj_232
LUT4 --- 0.448 D to Z \VGA_inst/i1_4_lut_adj_17
Route 1 e 0.788 \VGA_inst/n987
LUT4 --- 0.448 B to Z \VGA_inst/i4_4_lut_adj_15
Route 23 e 1.533 \VGA_inst/Clock_c_enable_50
LUT4 --- 0.448 D to Z \VGA_inst/i1_2_lut_rep_9_4_lut
Route 18 e 1.521 \VGA_inst/Clock_c_enable_52
LUT4 --- 0.448 A to Z \VGA_inst/i363_4_lut
Route 3 e 1.051 \VGA_inst/n454
--------
9.627 (27.5% logic, 72.5% route), 6 logic levels.
Error: The following path violates requirements by 4.773ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FD1S3IX CK \VGA_inst/HCounter_83__i4 (from Clock_c +)
Destination: FD1P3IX CD \VGA_inst/VDivider_86__i0 (to Clock_c +)
Delay: 9.627ns (27.5% logic, 72.5% route), 6 logic levels.
Constraint Details:
9.627ns data_path \VGA_inst/HCounter_83__i4 to \VGA_inst/VDivider_86__i0 violates
5.000ns delay constraint less
0.146ns L_S requirement (totaling 4.854ns) by 4.773ns
Path Details: \VGA_inst/HCounter_83__i4 to \VGA_inst/VDivider_86__i0
Name Fanout Delay (ns) Pins Resource(Cell.Net)
L_CO --- 0.403 CK to Q \VGA_inst/HCounter_83__i4 (from Clock_c)
Route 7 e 1.303 \VGA_inst/HCounter[4]
LUT4 --- 0.448 A to Z \VGA_inst/i1_2_lut_adj_18
Route 1 e 0.788 \VGA_inst/n4_adj_232
LUT4 --- 0.448 D to Z \VGA_inst/i1_4_lut_adj_17
Route 1 e 0.788 \VGA_inst/n987
LUT4 --- 0.448 B to Z \VGA_inst/i4_4_lut_adj_15
Route 23 e 1.533 \VGA_inst/Clock_c_enable_50
LUT4 --- 0.448 D to Z \VGA_inst/i1_2_lut_rep_9_4_lut
Route 18 e 1.521 \VGA_inst/Clock_c_enable_52
LUT4 --- 0.448 A to Z \VGA_inst/i363_4_lut
Route 3 e 1.051 \VGA_inst/n454
--------
9.627 (27.5% logic, 72.5% route), 6 logic levels.
Warning: 9.773 ns is the maximum delay for this constraint.
Timing Report Summary
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Constraint | Constraint| Actual|Levels
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| | |
create_clock -period 5.000000 -name | | |
clk0 [get_nets Clock_c] | 5.000 ns| 9.773 ns| 6 *
| | |
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1 constraints not met.
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Critical Nets | Loads| Errors| % of total
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\VGA_inst/Clock_c_enable_50 | 23| 520| 58.62%
| | |
\VGA_inst/n987 | 1| 275| 31.00%
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\VGA_inst/Clock_c_enable_52 | 18| 209| 23.56%
| | |
\VGA_inst/n438 | 10| 190| 21.42%
| | |
\VGA_inst/n89 | 3| 170| 19.17%
| | |
\VGA_inst/n456 | 7| 147| 16.57%
| | |
\VGA_inst/n412 | 5| 134| 15.11%
| | |
\VGA_inst/n4_adj_232 | 1| 114| 12.85%
| | |
\VGA_inst/n15 | 1| 100| 11.27%
| | |
\VGA_inst/n7 | 1| 94| 10.60%
| | |
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Timing summary:
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Timing errors: 887 Score: 1508777
Constraints cover 1593 paths, 230 nets, and 611 connections (97.9% coverage)
Peak memory: 58482688 bytes, TRCE: 1994752 bytes, DLYMAN: 0 bytes
CPU_TIME_REPORT: 0 secs