Setting log file to 'C:/Lattice/Kurs28/impl1/hdla_gen_hierarchy.html'.
Starting: parse design source files
(VERI-1482) Analyzing Verilog file 'C:/lscc/diamond/3.13/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v'
(VERI-1482) Analyzing Verilog file 'C:/Lattice/Kurs28/impl1/source/top.v'
(VERI-1482) Analyzing Verilog file 'C:/Lattice/Kurs28/impl1/source/slave_spi.v'
(VERI-1482) Analyzing Verilog file 'C:/Lattice/Kurs28/impl1/source/synchronizer.v'
(VERI-1482) Analyzing Verilog file 'C:/Lattice/Kurs28/impl1/source/edge_detector.v'
(VERI-1482) Analyzing Verilog file 'C:/Lattice/Kurs28/impl1/source/ram_pdp.v'
(VERI-1482) Analyzing Verilog file 'C:/Lattice/Kurs28/impl1/source/vga.v'
INFO - C:/Lattice/Kurs28/impl1/source/top.v(4,8-4,11) (VERI-1018) compiling module 'top'
INFO - C:/Lattice/Kurs28/impl1/source/top.v(4,1-93,10) (VERI-9000) elaborating module 'top'
INFO - C:/Lattice/Kurs28/impl1/source/slave_spi.v(5,1-105,10) (VERI-9000) elaborating module 'SlaveSPI_uniq_1'
INFO - C:/Lattice/Kurs28/impl1/source/synchronizer.v(4,1-28,10) (VERI-9000) elaborating module 'Synchronizer_uniq_2'
INFO - C:/Lattice/Kurs28/impl1/source/ram_pdp.v(4,1-51,10) (VERI-9000) elaborating module 'PseudoDualPortRAM_uniq_1'
INFO - C:/Lattice/Kurs28/impl1/source/vga.v(4,1-125,10) (VERI-9000) elaborating module 'VGA_uniq_1'
INFO - C:/Lattice/Kurs28/impl1/source/synchronizer.v(4,1-28,10) (VERI-9000) elaborating module 'Synchronizer_uniq_1'
INFO - C:/Lattice/Kurs28/impl1/source/edge_detector.v(4,1-24,10) (VERI-9000) elaborating module 'EdgeDetector_uniq_1'
INFO - C:/Lattice/Kurs28/impl1/source/edge_detector.v(4,1-24,10) (VERI-9000) elaborating module 'EdgeDetector_uniq_2'
Done: design load finished with (0) errors, and (0) warnings