Place & Route TRACE Report
Loading design for application trce from file kurs28_impl1.ncd.
Design name: top
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-1200HC
Package: TQFP100
Performance: 5
Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.13/ispfpga.
Package Status: Final Version 1.44.
Performance Hardware Data Status: Final Version 34.4.
Setup and Hold Report
--------------------------------------------------------------------------------
Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.13.0.56.2
Thu Oct 24 20:16:04 2024
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2023 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 10 -gt -sethld -sp 5 -sphld m -o Kurs28_impl1.twr -gui -msgset C:/Lattice/Kurs28/promote.xml Kurs28_impl1.ncd Kurs28_impl1.prf
Design file: kurs28_impl1.ncd
Preference file: kurs28_impl1.prf
Device,speed: LCMXO2-1200HC,5
Report level: verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------
Preference Summary
FREQUENCY PORT "Clock" 25.000000 MHz (0 errors) 1164 items scored, 0 timing errors detected.
Report: 108.155MHz is the maximum frequency for this preference.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
Derating parameters
-------------------
Voltage: 3.300 V
================================================================================
Preference: FREQUENCY PORT "Clock" 25.000000 MHz ;
1164 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 30.754ns
The internal maximum frequency of the following component is 108.155 MHz
Logical Details: Cell type Pin name Component name
Destination: DP8KC CLKA BitmapRAM/Memory0
Delay: 9.246ns -- based on Minimum Pulse Width
Passed: The following path meets requirements by 30.979ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: DP8KC Port BitmapRAM/Memory1(ASIC) (from Clock_c +)
Destination: FF Data in VGA_inst/Blue_o_86 (to Clock_c +)
Delay: 8.718ns (72.2% logic, 27.8% route), 5 logic levels.
Constraint Details:
8.718ns physical path delay BitmapRAM/Memory1 to VGA_inst/SLICE_27 meets
40.000ns delay constraint less
0.153ns skew and
0.150ns DIN_SET requirement (totaling 39.697ns) by 30.979ns
Physical Path Details:
Data path BitmapRAM/Memory1 to VGA_inst/SLICE_27:
Name Fanout Delay (ns) Site Resource
C2Q_DEL --- 4.739 EBR_R6C7.CLKB to EBR_R6C7.DOB1 BitmapRAM/Memory1 (from Clock_c)
ROUTE 1 1.855 EBR_R6C7.DOB1 to R5C11D.B1 n242
CTOOFX_DEL --- 0.661 R5C11D.B1 to R5C11D.OFX0 VGA_inst/i929/SLICE_51
ROUTE 1 0.000 R5C11D.OFX0 to R5C11C.FXA VGA_inst/n1038
FXTOOFX_DE --- 0.223 R5C11C.FXA to R5C11C.OFX1 VGA_inst/i930/SLICE_52
ROUTE 1 0.000 R5C11C.OFX1 to R5C11B.FXA VGA_inst/n1042
FXTOOFX_DE --- 0.223 R5C11B.FXA to R5C11B.OFX1 VGA_inst/SLICE_33
ROUTE 2 0.565 R5C11B.OFX1 to R5C10B.D0 VGA_inst/Red_o_N_186
CTOF_DEL --- 0.452 R5C10B.D0 to R5C10B.F0 VGA_inst/SLICE_27
ROUTE 1 0.000 R5C10B.F0 to R5C10B.DI0 VGA_inst/Red_o_N_198 (to Clock_c)
--------
8.718 (72.2% logic, 27.8% route), 5 logic levels.
Clock Skew Details:
Source Clock Path Clock to BitmapRAM/Memory1:
Name Fanout Delay (ns) Site Resource
ROUTE 51 2.154 20.PADDI to EBR_R6C7.CLKB Clock_c
--------
2.154 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path Clock to VGA_inst/SLICE_27:
Name Fanout Delay (ns) Site Resource
ROUTE 51 2.001 20.PADDI to R5C10B.CLK Clock_c
--------
2.001 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 31.058ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: DP8KC Port BitmapRAM/Memory1(ASIC) (from Clock_c +)
Destination: FF Data in VGA_inst/Blue_o_86 (to Clock_c +)
Delay: 8.639ns (72.9% logic, 27.1% route), 5 logic levels.
Constraint Details:
8.639ns physical path delay BitmapRAM/Memory1 to VGA_inst/SLICE_27 meets
40.000ns delay constraint less
0.153ns skew and
0.150ns DIN_SET requirement (totaling 39.697ns) by 31.058ns
Physical Path Details:
Data path BitmapRAM/Memory1 to VGA_inst/SLICE_27:
Name Fanout Delay (ns) Site Resource
C2Q_DEL --- 4.739 EBR_R6C7.CLKB to EBR_R6C7.DOB3 BitmapRAM/Memory1 (from Clock_c)
ROUTE 1 1.776 EBR_R6C7.DOB3 to R5C11C.C1 n244
CTOOFX_DEL --- 0.661 R5C11C.C1 to R5C11C.OFX0 VGA_inst/i930/SLICE_52
ROUTE 1 0.000 R5C11C.OFX0 to R5C11C.FXB VGA_inst/n1039
FXTOOFX_DE --- 0.223 R5C11C.FXB to R5C11C.OFX1 VGA_inst/i930/SLICE_52
ROUTE 1 0.000 R5C11C.OFX1 to R5C11B.FXA VGA_inst/n1042
FXTOOFX_DE --- 0.223 R5C11B.FXA to R5C11B.OFX1 VGA_inst/SLICE_33
ROUTE 2 0.565 R5C11B.OFX1 to R5C10B.D0 VGA_inst/Red_o_N_186
CTOF_DEL --- 0.452 R5C10B.D0 to R5C10B.F0 VGA_inst/SLICE_27
ROUTE 1 0.000 R5C10B.F0 to R5C10B.DI0 VGA_inst/Red_o_N_198 (to Clock_c)
--------
8.639 (72.9% logic, 27.1% route), 5 logic levels.
Clock Skew Details:
Source Clock Path Clock to BitmapRAM/Memory1:
Name Fanout Delay (ns) Site Resource
ROUTE 51 2.154 20.PADDI to EBR_R6C7.CLKB Clock_c
--------
2.154 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path Clock to VGA_inst/SLICE_27:
Name Fanout Delay (ns) Site Resource
ROUTE 51 2.001 20.PADDI to R5C10B.CLK Clock_c
--------
2.001 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 31.133ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: DP8KC Port BitmapRAM/Memory1(ASIC) (from Clock_c +)
Destination: FF Data in VGA_inst/Blue_o_86 (to Clock_c +)
Delay: 8.564ns (73.5% logic, 26.5% route), 5 logic levels.
Constraint Details:
8.564ns physical path delay BitmapRAM/Memory1 to VGA_inst/SLICE_27 meets
40.000ns delay constraint less
0.153ns skew and
0.150ns DIN_SET requirement (totaling 39.697ns) by 31.133ns
Physical Path Details:
Data path BitmapRAM/Memory1 to VGA_inst/SLICE_27:
Name Fanout Delay (ns) Site Resource
C2Q_DEL --- 4.739 EBR_R6C7.CLKB to EBR_R6C7.DOB2 BitmapRAM/Memory1 (from Clock_c)
ROUTE 1 1.701 EBR_R6C7.DOB2 to R5C11C.C0 n243
CTOOFX_DEL --- 0.661 R5C11C.C0 to R5C11C.OFX0 VGA_inst/i930/SLICE_52
ROUTE 1 0.000 R5C11C.OFX0 to R5C11C.FXB VGA_inst/n1039
FXTOOFX_DE --- 0.223 R5C11C.FXB to R5C11C.OFX1 VGA_inst/i930/SLICE_52
ROUTE 1 0.000 R5C11C.OFX1 to R5C11B.FXA VGA_inst/n1042
FXTOOFX_DE --- 0.223 R5C11B.FXA to R5C11B.OFX1 VGA_inst/SLICE_33
ROUTE 2 0.565 R5C11B.OFX1 to R5C10B.D0 VGA_inst/Red_o_N_186
CTOF_DEL --- 0.452 R5C10B.D0 to R5C10B.F0 VGA_inst/SLICE_27
ROUTE 1 0.000 R5C10B.F0 to R5C10B.DI0 VGA_inst/Red_o_N_198 (to Clock_c)
--------
8.564 (73.5% logic, 26.5% route), 5 logic levels.
Clock Skew Details:
Source Clock Path Clock to BitmapRAM/Memory1:
Name Fanout Delay (ns) Site Resource
ROUTE 51 2.154 20.PADDI to EBR_R6C7.CLKB Clock_c
--------
2.154 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path Clock to VGA_inst/SLICE_27:
Name Fanout Delay (ns) Site Resource
ROUTE 51 2.001 20.PADDI to R5C10B.CLK Clock_c
--------
2.001 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 31.248ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: DP8KC Port BitmapRAM/Memory1(ASIC) (from Clock_c +)
Destination: FF Data in VGA_inst/Blue_o_86 (to Clock_c +)
Delay: 8.449ns (74.5% logic, 25.5% route), 5 logic levels.
Constraint Details:
8.449ns physical path delay BitmapRAM/Memory1 to VGA_inst/SLICE_27 meets
40.000ns delay constraint less
0.153ns skew and
0.150ns DIN_SET requirement (totaling 39.697ns) by 31.248ns
Physical Path Details:
Data path BitmapRAM/Memory1 to VGA_inst/SLICE_27:
Name Fanout Delay (ns) Site Resource
C2Q_DEL --- 4.739 EBR_R6C7.CLKB to EBR_R6C7.DOB0 BitmapRAM/Memory1 (from Clock_c)
ROUTE 1 1.586 EBR_R6C7.DOB0 to R5C11D.D0 n241
CTOOFX_DEL --- 0.661 R5C11D.D0 to R5C11D.OFX0 VGA_inst/i929/SLICE_51
ROUTE 1 0.000 R5C11D.OFX0 to R5C11C.FXA VGA_inst/n1038
FXTOOFX_DE --- 0.223 R5C11C.FXA to R5C11C.OFX1 VGA_inst/i930/SLICE_52
ROUTE 1 0.000 R5C11C.OFX1 to R5C11B.FXA VGA_inst/n1042
FXTOOFX_DE --- 0.223 R5C11B.FXA to R5C11B.OFX1 VGA_inst/SLICE_33
ROUTE 2 0.565 R5C11B.OFX1 to R5C10B.D0 VGA_inst/Red_o_N_186
CTOF_DEL --- 0.452 R5C10B.D0 to R5C10B.F0 VGA_inst/SLICE_27
ROUTE 1 0.000 R5C10B.F0 to R5C10B.DI0 VGA_inst/Red_o_N_198 (to Clock_c)
--------
8.449 (74.5% logic, 25.5% route), 5 logic levels.
Clock Skew Details:
Source Clock Path Clock to BitmapRAM/Memory1:
Name Fanout Delay (ns) Site Resource
ROUTE 51 2.154 20.PADDI to EBR_R6C7.CLKB Clock_c
--------
2.154 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path Clock to VGA_inst/SLICE_27:
Name Fanout Delay (ns) Site Resource
ROUTE 51 2.001 20.PADDI to R5C10B.CLK Clock_c
--------
2.001 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 31.492ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: DP8KC Port BitmapRAM/Memory0(ASIC) (from Clock_c +)
Destination: FF Data in VGA_inst/Blue_o_86 (to Clock_c +)
Delay: 8.205ns (76.8% logic, 23.2% route), 5 logic levels.
Constraint Details:
8.205ns physical path delay BitmapRAM/Memory0 to VGA_inst/SLICE_27 meets
40.000ns delay constraint less
0.153ns skew and
0.150ns DIN_SET requirement (totaling 39.697ns) by 31.492ns
Physical Path Details:
Data path BitmapRAM/Memory0 to VGA_inst/SLICE_27:
Name Fanout Delay (ns) Site Resource
C2Q_DEL --- 4.739 EBR_R6C10.CLKB to EBR_R6C10.DOB0 BitmapRAM/Memory0 (from Clock_c)
ROUTE 1 1.342 EBR_R6C10.DOB0 to R5C11D.A0 n233
CTOOFX_DEL --- 0.661 R5C11D.A0 to R5C11D.OFX0 VGA_inst/i929/SLICE_51
ROUTE 1 0.000 R5C11D.OFX0 to R5C11C.FXA VGA_inst/n1038
FXTOOFX_DE --- 0.223 R5C11C.FXA to R5C11C.OFX1 VGA_inst/i930/SLICE_52
ROUTE 1 0.000 R5C11C.OFX1 to R5C11B.FXA VGA_inst/n1042
FXTOOFX_DE --- 0.223 R5C11B.FXA to R5C11B.OFX1 VGA_inst/SLICE_33
ROUTE 2 0.565 R5C11B.OFX1 to R5C10B.D0 VGA_inst/Red_o_N_186
CTOF_DEL --- 0.452 R5C10B.D0 to R5C10B.F0 VGA_inst/SLICE_27
ROUTE 1 0.000 R5C10B.F0 to R5C10B.DI0 VGA_inst/Red_o_N_198 (to Clock_c)
--------
8.205 (76.8% logic, 23.2% route), 5 logic levels.
Clock Skew Details:
Source Clock Path Clock to BitmapRAM/Memory0:
Name Fanout Delay (ns) Site Resource
ROUTE 51 2.154 20.PADDI to EBR_R6C10.CLKB Clock_c
--------
2.154 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path Clock to VGA_inst/SLICE_27:
Name Fanout Delay (ns) Site Resource
ROUTE 51 2.001 20.PADDI to R5C10B.CLK Clock_c
--------
2.001 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 31.492ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: DP8KC Port BitmapRAM/Memory1(ASIC) (from Clock_c +)
Destination: FF Data in VGA_inst/Blue_o_86 (to Clock_c +)
Delay: 8.205ns (76.8% logic, 23.2% route), 5 logic levels.
Constraint Details:
8.205ns physical path delay BitmapRAM/Memory1 to VGA_inst/SLICE_27 meets
40.000ns delay constraint less
0.153ns skew and
0.150ns DIN_SET requirement (totaling 39.697ns) by 31.492ns
Physical Path Details:
Data path BitmapRAM/Memory1 to VGA_inst/SLICE_27:
Name Fanout Delay (ns) Site Resource
C2Q_DEL --- 4.739 EBR_R6C7.CLKB to EBR_R6C7.DOB6 BitmapRAM/Memory1 (from Clock_c)
ROUTE 1 1.342 EBR_R6C7.DOB6 to R5C11A.A0 n247
CTOOFX_DEL --- 0.661 R5C11A.A0 to R5C11A.OFX0 VGA_inst/i932/SLICE_53
ROUTE 1 0.000 R5C11A.OFX0 to R5C11A.FXB VGA_inst/n1041
FXTOOFX_DE --- 0.223 R5C11A.FXB to R5C11A.OFX1 VGA_inst/i932/SLICE_53
ROUTE 1 0.000 R5C11A.OFX1 to R5C11B.FXB VGA_inst/n1043
FXTOOFX_DE --- 0.223 R5C11B.FXB to R5C11B.OFX1 VGA_inst/SLICE_33
ROUTE 2 0.565 R5C11B.OFX1 to R5C10B.D0 VGA_inst/Red_o_N_186
CTOF_DEL --- 0.452 R5C10B.D0 to R5C10B.F0 VGA_inst/SLICE_27
ROUTE 1 0.000 R5C10B.F0 to R5C10B.DI0 VGA_inst/Red_o_N_198 (to Clock_c)
--------
8.205 (76.8% logic, 23.2% route), 5 logic levels.
Clock Skew Details:
Source Clock Path Clock to BitmapRAM/Memory1:
Name Fanout Delay (ns) Site Resource
ROUTE 51 2.154 20.PADDI to EBR_R6C7.CLKB Clock_c
--------
2.154 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path Clock to VGA_inst/SLICE_27:
Name Fanout Delay (ns) Site Resource
ROUTE 51 2.001 20.PADDI to R5C10B.CLK Clock_c
--------
2.001 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 31.492ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: DP8KC Port BitmapRAM/Memory0(ASIC) (from Clock_c +)
Destination: FF Data in VGA_inst/Blue_o_86 (to Clock_c +)
Delay: 8.205ns (76.8% logic, 23.2% route), 5 logic levels.
Constraint Details:
8.205ns physical path delay BitmapRAM/Memory0 to VGA_inst/SLICE_27 meets
40.000ns delay constraint less
0.153ns skew and
0.150ns DIN_SET requirement (totaling 39.697ns) by 31.492ns
Physical Path Details:
Data path BitmapRAM/Memory0 to VGA_inst/SLICE_27:
Name Fanout Delay (ns) Site Resource
C2Q_DEL --- 4.739 EBR_R6C10.CLKB to EBR_R6C10.DOB7 BitmapRAM/Memory0 (from Clock_c)
ROUTE 1 1.342 EBR_R6C10.DOB7 to R5C11A.A1 n240
CTOOFX_DEL --- 0.661 R5C11A.A1 to R5C11A.OFX0 VGA_inst/i932/SLICE_53
ROUTE 1 0.000 R5C11A.OFX0 to R5C11A.FXB VGA_inst/n1041
FXTOOFX_DE --- 0.223 R5C11A.FXB to R5C11A.OFX1 VGA_inst/i932/SLICE_53
ROUTE 1 0.000 R5C11A.OFX1 to R5C11B.FXB VGA_inst/n1043
FXTOOFX_DE --- 0.223 R5C11B.FXB to R5C11B.OFX1 VGA_inst/SLICE_33
ROUTE 2 0.565 R5C11B.OFX1 to R5C10B.D0 VGA_inst/Red_o_N_186
CTOF_DEL --- 0.452 R5C10B.D0 to R5C10B.F0 VGA_inst/SLICE_27
ROUTE 1 0.000 R5C10B.F0 to R5C10B.DI0 VGA_inst/Red_o_N_198 (to Clock_c)
--------
8.205 (76.8% logic, 23.2% route), 5 logic levels.
Clock Skew Details:
Source Clock Path Clock to BitmapRAM/Memory0:
Name Fanout Delay (ns) Site Resource
ROUTE 51 2.154 20.PADDI to EBR_R6C10.CLKB Clock_c
--------
2.154 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path Clock to VGA_inst/SLICE_27:
Name Fanout Delay (ns) Site Resource
ROUTE 51 2.001 20.PADDI to R5C10B.CLK Clock_c
--------
2.001 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 31.512ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: DP8KC Port BitmapRAM/Memory1(ASIC) (from Clock_c +)
Destination: FF Data in VGA_inst/Blue_o_86 (to Clock_c +)
Delay: 8.185ns (76.9% logic, 23.1% route), 5 logic levels.
Constraint Details:
8.185ns physical path delay BitmapRAM/Memory1 to VGA_inst/SLICE_27 meets
40.000ns delay constraint less
0.153ns skew and
0.150ns DIN_SET requirement (totaling 39.697ns) by 31.512ns
Physical Path Details:
Data path BitmapRAM/Memory1 to VGA_inst/SLICE_27:
Name Fanout Delay (ns) Site Resource
C2Q_DEL --- 4.739 EBR_R6C7.CLKB to EBR_R6C7.DOB5 BitmapRAM/Memory1 (from Clock_c)
ROUTE 1 1.322 EBR_R6C7.DOB5 to R5C11B.C1 n246
CTOOFX_DEL --- 0.661 R5C11B.C1 to R5C11B.OFX0 VGA_inst/SLICE_33
ROUTE 1 0.000 R5C11B.OFX0 to R5C11A.FXA VGA_inst/n1040
FXTOOFX_DE --- 0.223 R5C11A.FXA to R5C11A.OFX1 VGA_inst/i932/SLICE_53
ROUTE 1 0.000 R5C11A.OFX1 to R5C11B.FXB VGA_inst/n1043
FXTOOFX_DE --- 0.223 R5C11B.FXB to R5C11B.OFX1 VGA_inst/SLICE_33
ROUTE 2 0.565 R5C11B.OFX1 to R5C10B.D0 VGA_inst/Red_o_N_186
CTOF_DEL --- 0.452 R5C10B.D0 to R5C10B.F0 VGA_inst/SLICE_27
ROUTE 1 0.000 R5C10B.F0 to R5C10B.DI0 VGA_inst/Red_o_N_198 (to Clock_c)
--------
8.185 (76.9% logic, 23.1% route), 5 logic levels.
Clock Skew Details:
Source Clock Path Clock to BitmapRAM/Memory1:
Name Fanout Delay (ns) Site Resource
ROUTE 51 2.154 20.PADDI to EBR_R6C7.CLKB Clock_c
--------
2.154 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path Clock to VGA_inst/SLICE_27:
Name Fanout Delay (ns) Site Resource
ROUTE 51 2.001 20.PADDI to R5C10B.CLK Clock_c
--------
2.001 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 31.512ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: DP8KC Port BitmapRAM/Memory1(ASIC) (from Clock_c +)
Destination: FF Data in VGA_inst/Blue_o_86 (to Clock_c +)
Delay: 8.185ns (76.9% logic, 23.1% route), 5 logic levels.
Constraint Details:
8.185ns physical path delay BitmapRAM/Memory1 to VGA_inst/SLICE_27 meets
40.000ns delay constraint less
0.153ns skew and
0.150ns DIN_SET requirement (totaling 39.697ns) by 31.512ns
Physical Path Details:
Data path BitmapRAM/Memory1 to VGA_inst/SLICE_27:
Name Fanout Delay (ns) Site Resource
C2Q_DEL --- 4.739 EBR_R6C7.CLKB to EBR_R6C7.DOB4 BitmapRAM/Memory1 (from Clock_c)
ROUTE 1 1.322 EBR_R6C7.DOB4 to R5C11B.C0 n245
CTOOFX_DEL --- 0.661 R5C11B.C0 to R5C11B.OFX0 VGA_inst/SLICE_33
ROUTE 1 0.000 R5C11B.OFX0 to R5C11A.FXA VGA_inst/n1040
FXTOOFX_DE --- 0.223 R5C11A.FXA to R5C11A.OFX1 VGA_inst/i932/SLICE_53
ROUTE 1 0.000 R5C11A.OFX1 to R5C11B.FXB VGA_inst/n1043
FXTOOFX_DE --- 0.223 R5C11B.FXB to R5C11B.OFX1 VGA_inst/SLICE_33
ROUTE 2 0.565 R5C11B.OFX1 to R5C10B.D0 VGA_inst/Red_o_N_186
CTOF_DEL --- 0.452 R5C10B.D0 to R5C10B.F0 VGA_inst/SLICE_27
ROUTE 1 0.000 R5C10B.F0 to R5C10B.DI0 VGA_inst/Red_o_N_198 (to Clock_c)
--------
8.185 (76.9% logic, 23.1% route), 5 logic levels.
Clock Skew Details:
Source Clock Path Clock to BitmapRAM/Memory1:
Name Fanout Delay (ns) Site Resource
ROUTE 51 2.154 20.PADDI to EBR_R6C7.CLKB Clock_c
--------
2.154 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path Clock to VGA_inst/SLICE_27:
Name Fanout Delay (ns) Site Resource
ROUTE 51 2.001 20.PADDI to R5C10B.CLK Clock_c
--------
2.001 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 31.604ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q VGA_inst/HCounter_83__i3 (from Clock_c +)
Destination: FF Data in VGA_inst/Blue_o_86 (to Clock_c +)
Delay: 8.147ns (31.4% logic, 68.6% route), 6 logic levels.
Constraint Details:
8.147ns physical path delay VGA_inst/SLICE_23 to VGA_inst/SLICE_27 meets
40.000ns delay constraint less
0.000ns skew and
0.249ns CE_SET requirement (totaling 39.751ns) by 31.604ns
Physical Path Details:
Data path VGA_inst/SLICE_23 to VGA_inst/SLICE_27:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R9C12C.CLK to R9C12C.Q0 VGA_inst/SLICE_23 (from Clock_c)
ROUTE 6 1.366 R9C12C.Q0 to R8C12D.C0 VGA_inst/HCounter_3
CTOF_DEL --- 0.452 R8C12D.C0 to R8C12D.F0 SLICE_67
ROUTE 2 0.511 R8C12D.F0 to R8C12A.M0 VGA_inst/n1097
MTOOFX_DEL --- 0.345 R8C12A.M0 to R8C12A.OFX0 VGA_inst/i947/SLICE_54
ROUTE 1 0.544 R8C12A.OFX0 to R8C12C.D0 VGA_inst/n1056
CTOF_DEL --- 0.452 R8C12C.D0 to R8C12C.F0 VGA_inst/SLICE_71
ROUTE 1 1.471 R8C12C.F0 to R7C11B.C0 VGA_inst/n1057
CTOF_DEL --- 0.452 R7C11B.C0 to R7C11B.F0 SLICE_61
ROUTE 3 0.399 R7C11B.F0 to R7C11B.C1 VGA_inst/n169
CTOF_DEL --- 0.452 R7C11B.C1 to R7C11B.F1 SLICE_61
ROUTE 3 1.294 R7C11B.F1 to R5C10B.CE VGA_inst/Clock_c_enable_25 (to Clock_c)
--------
8.147 (31.4% logic, 68.6% route), 6 logic levels.
Clock Skew Details:
Source Clock Path Clock to VGA_inst/SLICE_23:
Name Fanout Delay (ns) Site Resource
ROUTE 51 2.001 20.PADDI to R9C12C.CLK Clock_c
--------
2.001 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path Clock to VGA_inst/SLICE_27:
Name Fanout Delay (ns) Site Resource
ROUTE 51 2.001 20.PADDI to R5C10B.CLK Clock_c
--------
2.001 (0.0% logic, 100.0% route), 0 logic levels.
Report: 108.155MHz is the maximum frequency for this preference.
Report Summary
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY PORT "Clock" 25.000000 MHz ; | 25.000 MHz| 108.155 MHz| 0
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 1 clocks:
Clock Domain: Clock_c Source: Clock.PAD Loads: 51
Covered under: FREQUENCY PORT "Clock" 25.000000 MHz ;
Timing summary (Setup):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 1164 paths, 1 nets, and 528 connections (97.96% coverage)
--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.13.0.56.2
Thu Oct 24 20:16:04 2024
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2023 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 10 -gt -sethld -sp 5 -sphld m -o Kurs28_impl1.twr -gui -msgset C:/Lattice/Kurs28/promote.xml Kurs28_impl1.ncd Kurs28_impl1.prf
Design file: kurs28_impl1.ncd
Preference file: kurs28_impl1.prf
Device,speed: LCMXO2-1200HC,m
Report level: verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------
Preference Summary
FREQUENCY PORT "Clock" 25.000000 MHz (0 errors) 1164 items scored, 0 timing errors detected.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
Derating parameters
-------------------
Voltage: 3.300 V
================================================================================
Preference: FREQUENCY PORT "Clock" 25.000000 MHz ;
1164 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.221ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q WriteAddress__i1 (from Clock_c +)
Destination: DP8KC Port BitmapRAM/Memory1(ASIC) (to Clock_c +)
Delay: 0.327ns (40.7% logic, 59.3% route), 1 logic levels.
Constraint Details:
0.327ns physical path delay SLICE_2 to BitmapRAM/Memory1 meets
0.052ns ADDR_HLD and
0.000ns delay constraint less
-0.054ns skew requirement (totaling 0.106ns) by 0.221ns
Physical Path Details:
Data path SLICE_2 to BitmapRAM/Memory1:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R7C9B.CLK to R7C9B.Q0 SLICE_2 (from Clock_c)
ROUTE 3 0.194 R7C9B.Q0 to EBR_R6C7.ADA4 WriteAddress_1 (to Clock_c)
--------
0.327 (40.7% logic, 59.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path Clock to SLICE_2:
Name Fanout Delay (ns) Site Resource
ROUTE 51 0.773 20.PADDI to R7C9B.CLK Clock_c
--------
0.773 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path Clock to BitmapRAM/Memory1:
Name Fanout Delay (ns) Site Resource
ROUTE 51 0.827 20.PADDI to EBR_R6C7.CLKA Clock_c
--------
0.827 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.221ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q WriteAddress__i2 (from Clock_c +)
Destination: DP8KC Port BitmapRAM/Memory1(ASIC) (to Clock_c +)
Delay: 0.327ns (40.7% logic, 59.3% route), 1 logic levels.
Constraint Details:
0.327ns physical path delay SLICE_2 to BitmapRAM/Memory1 meets
0.052ns ADDR_HLD and
0.000ns delay constraint less
-0.054ns skew requirement (totaling 0.106ns) by 0.221ns
Physical Path Details:
Data path SLICE_2 to BitmapRAM/Memory1:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R7C9B.CLK to R7C9B.Q1 SLICE_2 (from Clock_c)
ROUTE 3 0.194 R7C9B.Q1 to EBR_R6C7.ADA5 WriteAddress_2 (to Clock_c)
--------
0.327 (40.7% logic, 59.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path Clock to SLICE_2:
Name Fanout Delay (ns) Site Resource
ROUTE 51 0.773 20.PADDI to R7C9B.CLK Clock_c
--------
0.773 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path Clock to BitmapRAM/Memory1:
Name Fanout Delay (ns) Site Resource
ROUTE 51 0.827 20.PADDI to EBR_R6C7.CLKA Clock_c
--------
0.827 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.238ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q SlaveSPI_inst/DataReceived_o_i0_i7 (from Clock_c +)
Destination: DP8KC Port BitmapRAM/Memory0(ASIC) (to Clock_c +)
Delay: 0.343ns (38.8% logic, 61.2% route), 1 logic levels.
Constraint Details:
0.343ns physical path delay SLICE_60 to BitmapRAM/Memory0 meets
0.051ns DATA_HLD and
0.000ns delay constraint less
-0.054ns skew requirement (totaling 0.105ns) by 0.238ns
Physical Path Details:
Data path SLICE_60 to BitmapRAM/Memory0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R7C12C.CLK to R7C12C.Q1 SLICE_60 (from Clock_c)
ROUTE 2 0.210 R7C12C.Q1 to EBR_R6C10.DIA7 DataFromSPI_7 (to Clock_c)
--------
0.343 (38.8% logic, 61.2% route), 1 logic levels.
Clock Skew Details:
Source Clock Path Clock to SLICE_60:
Name Fanout Delay (ns) Site Resource
ROUTE 51 0.773 20.PADDI to R7C12C.CLK Clock_c
--------
0.773 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path Clock to BitmapRAM/Memory0:
Name Fanout Delay (ns) Site Resource
ROUTE 51 0.827 20.PADDI to EBR_R6C10.CLKA Clock_c
--------
0.827 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.241ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q SlaveSPI_inst/DataReceived_o_i0_i6 (from Clock_c +)
Destination: DP8KC Port BitmapRAM/Memory0(ASIC) (to Clock_c +)
Delay: 0.346ns (38.4% logic, 61.6% route), 1 logic levels.
Constraint Details:
0.346ns physical path delay SLICE_60 to BitmapRAM/Memory0 meets
0.051ns DATA_HLD and
0.000ns delay constraint less
-0.054ns skew requirement (totaling 0.105ns) by 0.241ns
Physical Path Details:
Data path SLICE_60 to BitmapRAM/Memory0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R7C12C.CLK to R7C12C.Q0 SLICE_60 (from Clock_c)
ROUTE 3 0.213 R7C12C.Q0 to EBR_R6C10.DIA6 DataFromSPI_6 (to Clock_c)
--------
0.346 (38.4% logic, 61.6% route), 1 logic levels.
Clock Skew Details:
Source Clock Path Clock to SLICE_60:
Name Fanout Delay (ns) Site Resource
ROUTE 51 0.773 20.PADDI to R7C12C.CLK Clock_c
--------
0.773 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path Clock to BitmapRAM/Memory0:
Name Fanout Delay (ns) Site Resource
ROUTE 51 0.827 20.PADDI to EBR_R6C10.CLKA Clock_c
--------
0.827 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.302ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q VGA_inst/VPixel_85__i3 (from Clock_c +)
Destination: DP8KC Port BitmapRAM/Memory0(ASIC) (to Clock_c +)
Delay: 0.428ns (31.1% logic, 68.9% route), 1 logic levels.
Constraint Details:
0.428ns physical path delay VGA_inst/SLICE_6 to BitmapRAM/Memory0 meets
0.072ns ADDR_HLD and
0.000ns delay constraint less
-0.054ns skew requirement (totaling 0.126ns) by 0.302ns
Physical Path Details:
Data path VGA_inst/SLICE_6 to BitmapRAM/Memory0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R5C12C.CLK to R5C12C.Q0 VGA_inst/SLICE_6 (from Clock_c)
ROUTE 3 0.295 R5C12C.Q0 to *R_R6C10.ADB10 ReadAddress_7 (to Clock_c)
--------
0.428 (31.1% logic, 68.9% route), 1 logic levels.
Clock Skew Details:
Source Clock Path Clock to VGA_inst/SLICE_6:
Name Fanout Delay (ns) Site Resource
ROUTE 51 0.773 20.PADDI to R5C12C.CLK Clock_c
--------
0.773 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path Clock to BitmapRAM/Memory0:
Name Fanout Delay (ns) Site Resource
ROUTE 51 0.827 20.PADDI to EBR_R6C10.CLKB Clock_c
--------
0.827 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.303ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q VGA_inst/VPixel_85__i4 (from Clock_c +)
Destination: DP8KC Port BitmapRAM/Memory0(ASIC) (to Clock_c +)
Delay: 0.429ns (31.0% logic, 69.0% route), 1 logic levels.
Constraint Details:
0.429ns physical path delay VGA_inst/SLICE_6 to BitmapRAM/Memory0 meets
0.072ns ADDR_HLD and
0.000ns delay constraint less
-0.054ns skew requirement (totaling 0.126ns) by 0.303ns
Physical Path Details:
Data path VGA_inst/SLICE_6 to BitmapRAM/Memory0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R5C12C.CLK to R5C12C.Q1 VGA_inst/SLICE_6 (from Clock_c)
ROUTE 3 0.296 R5C12C.Q1 to *R_R6C10.ADB11 ReadAddress_8 (to Clock_c)
--------
0.429 (31.0% logic, 69.0% route), 1 logic levels.
Clock Skew Details:
Source Clock Path Clock to VGA_inst/SLICE_6:
Name Fanout Delay (ns) Site Resource
ROUTE 51 0.773 20.PADDI to R5C12C.CLK Clock_c
--------
0.773 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path Clock to BitmapRAM/Memory0:
Name Fanout Delay (ns) Site Resource
ROUTE 51 0.827 20.PADDI to EBR_R6C10.CLKB Clock_c
--------
0.827 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.306ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q SlaveSPI_inst/DataReceived_o_i0_i6 (from Clock_c +)
Destination: FF Data in SlaveSPI_inst/DataReceived_o_i0_i7 (to Clock_c +)
Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels.
Constraint Details:
0.287ns physical path delay SLICE_60 to SLICE_60 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.306ns
Physical Path Details:
Data path SLICE_60 to SLICE_60:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R7C12C.CLK to R7C12C.Q0 SLICE_60 (from Clock_c)
ROUTE 3 0.154 R7C12C.Q0 to R7C12C.M1 DataFromSPI_6 (to Clock_c)
--------
0.287 (46.3% logic, 53.7% route), 1 logic levels.
Clock Skew Details:
Source Clock Path Clock to SLICE_60:
Name Fanout Delay (ns) Site Resource
ROUTE 51 0.773 20.PADDI to R7C12C.CLK Clock_c
--------
0.773 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path Clock to SLICE_60:
Name Fanout Delay (ns) Site Resource
ROUTE 51 0.773 20.PADDI to R7C12C.CLK Clock_c
--------
0.773 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.306ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q SlaveSPI_inst/DataReceived_o_i0_i0 (from Clock_c +)
Destination: FF Data in SlaveSPI_inst/DataReceived_o_i0_i1 (to Clock_c +)
Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels.
Constraint Details:
0.287ns physical path delay SlaveSPI_inst/SLICE_68 to SlaveSPI_inst/SLICE_68 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.306ns
Physical Path Details:
Data path SlaveSPI_inst/SLICE_68 to SlaveSPI_inst/SLICE_68:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R7C10C.CLK to R7C10C.Q0 SlaveSPI_inst/SLICE_68 (from Clock_c)
ROUTE 3 0.154 R7C10C.Q0 to R7C10C.M1 DataFromSPI_0 (to Clock_c)
--------
0.287 (46.3% logic, 53.7% route), 1 logic levels.
Clock Skew Details:
Source Clock Path Clock to SlaveSPI_inst/SLICE_68:
Name Fanout Delay (ns) Site Resource
ROUTE 51 0.773 20.PADDI to R7C10C.CLK Clock_c
--------
0.773 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path Clock to SlaveSPI_inst/SLICE_68:
Name Fanout Delay (ns) Site Resource
ROUTE 51 0.773 20.PADDI to R7C10C.CLK Clock_c
--------
0.773 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.307ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q SlaveSPI_inst/DataReceived_o_i0_i2 (from Clock_c +)
Destination: FF Data in SlaveSPI_inst/DataReceived_o_i0_i3 (to Clock_c +)
Delay: 0.288ns (46.2% logic, 53.8% route), 1 logic levels.
Constraint Details:
0.288ns physical path delay SlaveSPI_inst/SLICE_65 to SlaveSPI_inst/SLICE_65 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.307ns
Physical Path Details:
Data path SlaveSPI_inst/SLICE_65 to SlaveSPI_inst/SLICE_65:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R8C9B.CLK to R8C9B.Q0 SlaveSPI_inst/SLICE_65 (from Clock_c)
ROUTE 3 0.155 R8C9B.Q0 to R8C9B.M1 DataFromSPI_2 (to Clock_c)
--------
0.288 (46.2% logic, 53.8% route), 1 logic levels.
Clock Skew Details:
Source Clock Path Clock to SlaveSPI_inst/SLICE_65:
Name Fanout Delay (ns) Site Resource
ROUTE 51 0.773 20.PADDI to R8C9B.CLK Clock_c
--------
0.773 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path Clock to SlaveSPI_inst/SLICE_65:
Name Fanout Delay (ns) Site Resource
ROUTE 51 0.773 20.PADDI to R8C9B.CLK Clock_c
--------
0.773 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.316ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q SlaveSPI_inst/Synchronizer_inst/R2_i2 (from Clock_c +)
Destination: FF Data in SlaveSPI_inst/EdgeDetectorCS/Previous_13 (to Clock_c +)
Delay: 0.297ns (44.8% logic, 55.2% route), 1 logic levels.
Constraint Details:
0.297ns physical path delay SLICE_69 to SlaveSPI_inst/SLICE_44 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.316ns
Physical Path Details:
Data path SLICE_69 to SlaveSPI_inst/SLICE_44:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R8C11A.CLK to R8C11A.Q0 SLICE_69 (from Clock_c)
ROUTE 7 0.164 R8C11A.Q0 to R8C9A.M1 SyncCS (to Clock_c)
--------
0.297 (44.8% logic, 55.2% route), 1 logic levels.
Clock Skew Details:
Source Clock Path Clock to SLICE_69:
Name Fanout Delay (ns) Site Resource
ROUTE 51 0.773 20.PADDI to R8C11A.CLK Clock_c
--------
0.773 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path Clock to SlaveSPI_inst/SLICE_44:
Name Fanout Delay (ns) Site Resource
ROUTE 51 0.773 20.PADDI to R8C9A.CLK Clock_c
--------
0.773 (0.0% logic, 100.0% route), 0 logic levels.
Report Summary
--------------
----------------------------------------------------------------------------
Preference(MIN Delays) | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY PORT "Clock" 25.000000 MHz ; | -| -| 1
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 1 clocks:
Clock Domain: Clock_c Source: Clock.PAD Loads: 51
Covered under: FREQUENCY PORT "Clock" 25.000000 MHz ;
Timing summary (Hold):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 1164 paths, 1 nets, and 528 connections (97.96% coverage)
Timing summary (Setup and Hold):
---------------
Timing errors: 0 (setup), 0 (hold)
Score: 0 (setup), 0 (hold)
Cumulative negative slack: 0 (0+0)
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------