Lattice Mapping Report File for Design Module 'top'
Design Information
Command line: map -a MachXO2 -p LCMXO2-1200HC -t TQFP100 -s 5 -oc Commercial
Kurs28_impl1.ngd -o Kurs28_impl1_map.ncd -pr Kurs28_impl1.prf -mp
Kurs28_impl1.mrp -lpf C:/Lattice/Kurs28/impl1/Kurs28_impl1.lpf -lpf
C:/Lattice/Kurs28/Kurs28.lpf -c 0 -gui -msgset
C:/Lattice/Kurs28/promote.xml
Target Vendor: LATTICE
Target Device: LCMXO2-1200HCTQFP100
Target Performance: 5
Mapper: xo2c00, version: Diamond (64-bit) 3.13.0.56.2
Mapped on: 10/24/24 20:15:59
Design Summary
Number of registers: 78 out of 1520 (5%)
PFU registers: 78 out of 1280 (6%)
PIO registers: 0 out of 240 (0%)
Number of SLICEs: 59 out of 640 (9%)
SLICEs as Logic/ROM: 59 out of 640 (9%)
SLICEs as RAM: 0 out of 480 (0%)
SLICEs as Carry: 26 out of 640 (4%)
Number of LUT4s: 117 out of 1280 (9%)
Number used as logic LUTs: 65
Number used as distributed RAM: 0
Number used as ripple logic: 52
Number used as shift registers: 0
Number of PIO sites used: 11 + 4(JTAG) out of 80 (19%)
Number of block RAMs: 2 out of 7 (29%)
Number of GSRs: 1 out of 1 (100%)
EFB used : No
JTAG used : No
Readback used : No
Oscillator used : No
Startup used : No
POR : On
Bandgap : On
Number of Power Controller: 0 out of 1 (0%)
Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%)
Number of Dynamic Bank Controller (BCLVDSO): 0 out of 1 (0%)
Number of DCCA: 0 out of 8 (0%)
Number of DCMA: 0 out of 2 (0%)
Number of PLLs: 0 out of 1 (0%)
Number of DQSDLLs: 0 out of 2 (0%)
Number of CLKDIVC: 0 out of 4 (0%)
Number of ECLKSYNCA: 0 out of 4 (0%)
Number of ECLKBRIDGECS: 0 out of 2 (0%)
Notes:-
1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
distributed RAMs) + 2*(Number of ripple logic)
2. Number of logic LUT4s does not include count of distributed RAM and
ripple logic.
Number of clocks: 1
Net Clock_c: 51 loads, 51 rising, 0 falling (Driver: PIO Clock )
Number of Clock Enables: 8
Net Clock_c_enable_42: 6 loads, 6 LSLICEs
Net SlaveSPI_inst/Clock_c_enable_49: 4 loads, 4 LSLICEs
Net SlaveSPI_inst/Clock_c_enable_36: 1 loads, 1 LSLICEs
Net VGA_inst/Clock_c_enable_50: 6 loads, 6 LSLICEs
Net VGA_inst/Clock_c_enable_25: 3 loads, 3 LSLICEs
Net VGA_inst/Clock_c_enable_52: 6 loads, 6 LSLICEs
Net VGA_inst/Clock_c_enable_30: 4 loads, 4 LSLICEs
Net VGA_inst/Clock_c_enable_12: 1 loads, 1 LSLICEs
Number of LSRs: 10
Net n1101: 6 loads, 6 LSLICEs
Net SlaveSPI_inst/n179: 2 loads, 2 LSLICEs
Net Reset_c: 2 loads, 0 LSLICEs
Net VGA_inst/Clock_c_enable_50: 6 loads, 6 LSLICEs
Net VGA_inst/n438: 6 loads, 6 LSLICEs
Net VGA_inst/n169: 2 loads, 2 LSLICEs
Net VGA_inst/Clock_c_enable_52: 4 loads, 4 LSLICEs
Net VGA_inst/n456: 4 loads, 4 LSLICEs
Net VGA_inst/n454: 2 loads, 2 LSLICEs
Net VGA_inst/Clock_c_enable_30: 2 loads, 2 LSLICEs
Number of nets driven by tri-state buffers: 0
Top 10 highest fanout non-clock nets:
Net VGA_inst/Clock_c_enable_50: 15 loads
Net VGA_inst/Clock_c_enable_52: 11 loads
Net n249: 8 loads
Net VGA_inst/HCounter_7: 8 loads
Net SyncCS: 7 loads
Net VGA_inst/Clock_c_enable_30: 7 loads
Net VGA_inst/HCounter_1: 7 loads
Net VGA_inst/HCounter_4: 7 loads
Net VGA_inst/HCounter_9: 7 loads
Net Clock_c_enable_42: 6 loads
Number of warnings: 0
Number of errors: 0
Design Errors/Warnings
No errors or warnings present.
IO (PIO) Attributes
+---------------------+-----------+-----------+------------+
| IO Name | Direction | Levelmode | IO |
| | | IO_TYPE | Register |
+---------------------+-----------+-----------+------------+
| Clock | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| VSync_o | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Reset | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| HSync_o | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Blue_o | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Green_o | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Red_o | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| CS_i | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| SCK_i | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| MOSI_i | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| DC_i | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
Removed logic
Signal Reset_N_111 was merged into signal Reset_c
Signal GND_net undriven or does not drive anything - clipped.
Signal VCC_net undriven or does not drive anything - clipped.
Signal VGA_inst/VPixel_85_add_4_7/CO undriven or does not drive anything -
clipped.
Signal VGA_inst/HPixel_87_add_4_1/S0 undriven or does not drive anything -
clipped.
Signal VGA_inst/HPixel_87_add_4_1/CI undriven or does not drive anything -
clipped.
Signal VGA_inst/HCounter_83_add_4_1/S0 undriven or does not drive anything -
clipped.
Signal VGA_inst/HCounter_83_add_4_1/CI undriven or does not drive anything -
clipped.
Signal VGA_inst/HCounter_83_add_4_11/S1 undriven or does not drive anything -
clipped.
Signal VGA_inst/HCounter_83_add_4_11/CO undriven or does not drive anything -
clipped.
Signal VGA_inst/VCounter_84_add_4_1/S0 undriven or does not drive anything -
clipped.
Signal VGA_inst/VCounter_84_add_4_1/CI undriven or does not drive anything -
clipped.
Signal VGA_inst/HPixel_87_add_4_7/CO undriven or does not drive anything -
clipped.
Signal VGA_inst/VCounter_84_add_4_11/S1 undriven or does not drive anything -
clipped.
Signal VGA_inst/VCounter_84_add_4_11/CO undriven or does not drive anything -
clipped.
Signal VGA_inst/VPixel_85_add_4_1/S0 undriven or does not drive anything -
clipped.
Signal VGA_inst/VPixel_85_add_4_1/CI undriven or does not drive anything -
clipped.
Signal add_7_1/S0 undriven or does not drive anything - clipped.
Signal add_7_1/CI undriven or does not drive anything - clipped.
Signal add_7_11/CO undriven or does not drive anything - clipped.
Block SlaveSPI_inst/EdgeDetectorSCK/Reset_I_0_1_lut was optimized away.
Block i1 was optimized away.
Block i2 was optimized away.
Memory Usage
/BitmapRAM:
EBRs: 2
RAM SLICEs: 0
Logic SLICEs: 0
PFU Registers: 0
-Contains EBR Memory0: TYPE= DP8KC, Width_B= 8, Depth_A= 1024, Depth_B=
1024, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
ASYNC_RESET_RELEASE= ASYNC, WRITEMODE_A= READBEFOREWRITE,
WRITEMODE_B= READBEFOREWRITE, GSR= DISABLED
-Contains EBR Memory1: TYPE= DP8KC, Width_B= 8, Depth_A= 1024, Depth_B=
1024, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
ASYNC_RESET_RELEASE= ASYNC, WRITEMODE_A= READBEFOREWRITE,
WRITEMODE_B= READBEFOREWRITE, GSR= DISABLED
ASIC Components
---------------
Instance Name: BitmapRAM/Memory0
Type: DP8KC
Instance Name: BitmapRAM/Memory1
Type: DP8KC
GSR Usage
---------
GSR Component:
The Global Set Reset (GSR) resource has been used to implement a global reset
of the design. The reset signal used for GSR control is 'Reset_c'.
GSR Property:
The design components with GSR property set to ENABLED will respond to global
set reset while the components with GSR property set to DISABLED will
not.
Components with disabled GSR Property
-------------------------------------
These components have the GSR property set to DISABLED. The components will
not respond to the reset signal 'Reset_c' via the GSR component.
Type and number of components of the type:
Register = 1
DP8KC = 2
Type and instance name of component:
Register : BitmapRAM/_224
DP8KC : BitmapRAM/Memory0
DP8KC : BitmapRAM/Memory1
Components with synchronous local reset also reset by asynchronous GSR
----------------------------------------------------------------------
These components have the GSR property set to ENABLED and the local reset
is synchronous. The components will respond to the synchronous local reset
and to the unrelated asynchronous reset signal 'Reset_c' via the GSR
component.
Type and number of components of the type:
Register = 56
Type and instance name of component:
Register : WriteAddress__i4
Register : SlaveSPI_inst/BitCounter__i0
Register : SlaveSPI_inst/BitCounter__i2
Register : SlaveSPI_inst/BitCounter__i1
Register : WriteAddress__i3
Register : WriteAddress__i2
Register : WriteAddress__i1
Register : WriteAddress__i0
Register : WriteAddress__i10
Register : WriteAddress__i9
Register : WriteAddress__i8
Register : WriteAddress__i7
Register : WriteAddress__i6
Register : WriteAddress__i5
Register : VGA_inst/Red_o_88
Register : VGA_inst/VPixel_85__i3
Register : VGA_inst/VPixel_85__i4
Register : VGA_inst/VDivider_86__i1
Register : VGA_inst/HPixel_87__i2
Register : VGA_inst/HCounter_83__i0
Register : VGA_inst/VPixel_85__i5
Register : VGA_inst/HPixel_87__i4
Register : VGA_inst/VDivider_86__i2
Register : VGA_inst/HPixel_87__i3
Register : VGA_inst/VPixel_85__i6
Register : VGA_inst/HPixel_87__i5
Register : VGA_inst/HPixel_87__i6
Register : VGA_inst/HPixel_87__i7
Register : VGA_inst/VCounter_84__i0
Register : VGA_inst/VPixel_85__i0
Register : VGA_inst/VCounter_84__i2
Register : VGA_inst/VCounter_84__i1
Register : VGA_inst/VCounter_84__i3
Register : VGA_inst/VCounter_84__i4
Register : VGA_inst/VCounter_84__i5
Register : VGA_inst/Blue_o_86
Register : VGA_inst/VCounter_84__i6
Register : VGA_inst/VCounter_84__i8
Register : VGA_inst/VDivider_86__i0
Register : VGA_inst/VCounter_84__i7
Register : VGA_inst/HPixel_87__i1
Register : VGA_inst/HDivider_88__i2
Register : VGA_inst/HDivider_88__i1
Register : VGA_inst/HDivider_88__i0
Register : VGA_inst/HCounter_83__i9
Register : VGA_inst/HCounter_83__i8
Register : VGA_inst/HCounter_83__i7
Register : VGA_inst/HCounter_83__i6
Register : VGA_inst/HCounter_83__i5
Register : VGA_inst/HCounter_83__i4
Register : VGA_inst/HCounter_83__i3
Register : VGA_inst/HCounter_83__i2
Register : VGA_inst/HCounter_83__i1
Register : VGA_inst/VCounter_84__i9
Register : VGA_inst/VPixel_85__i2
Register : VGA_inst/VPixel_85__i1
Run Time and Memory Usage
-------------------------
Total CPU Time: 0 secs
Total REAL Time: 0 secs
Peak Memory Usage: 40 MB
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