Lattice Mapping Report File for Design Module 'top'



Design Information

Command line:   map -a MachXO2 -p LCMXO2-1200HC -t TQFP100 -s 5 -oc Commercial
     Kurs16_impl1.ngd -o Kurs16_impl1_map.ncd -pr Kurs16_impl1.prf -mp
     Kurs16_impl1.mrp -lpf C:/Lattice/Kurs16/impl1/Kurs16_impl1.lpf -lpf
     C:/Lattice/Kurs16/Kurs16.lpf -c 0 -gui 
Target Vendor:  LATTICE
Target Device:  LCMXO2-1200HCTQFP100
Target Performance:   5
Mapper:  xo2c00,  version:  Diamond (64-bit) 3.12.1.454
Mapped on:  09/23/23  12:00:31


Design Summary
   Number of registers:     54 out of  1520 (4%)
      PFU registers:           54 out of  1280 (4%)
      PIO registers:            0 out of   240 (0%)
   Number of SLICEs:        55 out of   640 (9%)
      SLICEs as Logic/ROM:     55 out of   640 (9%)
      SLICEs as RAM:            0 out of   480 (0%)
      SLICEs as Carry:         26 out of   640 (4%)
   Number of LUT4s:        109 out of  1280 (9%)
      Number used as logic LUTs:         57
      Number used as distributed RAM:     0
      Number used as ripple logic:       52
      Number used as shift registers:     0
   Number of PIO sites used: 5 + 4(JTAG) out of 80 (11%)
   Number of block RAMs:  0 out of 7 (0%)
   Number of GSRs:        1 out of 1 (100%)
   EFB used :        No
   JTAG used :       No
   Readback used :   No
   Oscillator used : Yes
   Startup used :    No
   POR :             On
   Bandgap :         On
   Number of Power Controller:  0 out of 1 (0%)
   Number of Dynamic Bank Controller (BCINRD):  0 out of 4 (0%)
   Number of Dynamic Bank Controller (BCLVDSO):  0 out of 1 (0%)
   Number of DCCA:  0 out of 8 (0%)
   Number of DCMA:  0 out of 2 (0%)
   Number of PLLs:  0 out of 1 (0%)
   Number of DQSDLLs:  0 out of 2 (0%)
   Number of CLKDIVC:  0 out of 4 (0%)
   Number of ECLKSYNCA:  0 out of 4 (0%)
   Number of ECLKBRIDGECS:  0 out of 2 (0%)
   Notes:-
      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
     distributed RAMs) + 2*(Number of ripple logic)
      2. Number of logic LUT4s does not include count of distributed RAM and
     ripple logic.
   Number of clocks:  1
     Net Clock: 33 loads, 33 rising, 0 falling (Driver: OSCH_inst )
   Number of Clock Enables:  5
     Net Play_i_c: 1 loads, 1 LSLICEs
     Net Clock_enable_6: 2 loads, 2 LSLICEs

     Net Clock_enable_11: 2 loads, 2 LSLICEs
     Net DUT/Clock_enable_20: 7 loads, 7 LSLICEs
     Net DUT/Clock_enable_4: 1 loads, 1 LSLICEs
   Number of LSRs:  4
     Net Play_i_c: 14 loads, 14 LSLICEs
     Net n40: 2 loads, 2 LSLICEs
     Net n37: 8 loads, 8 LSLICEs
     Net DUT/n126: 1 loads, 1 LSLICEs
   Number of nets driven by tri-state buffers:  0
   Top 10 highest fanout non-clock nets:
     Net Play_i_c: 30 loads
     Net Busy_o_c: 25 loads
     Net DUT/TickMilli: 17 loads
     Net n31: 17 loads
     Net Stop_i_c: 16 loads
     Net n37: 8 loads
     Net DUT/Clock_enable_20: 7 loads
     Net HalfPeriodCopy_6: 6 loads
     Net DUT/StrobeGeneratorMicro/Counter_0: 5 loads
     Net DUT/StrobeGeneratorMicro/Counter_1: 4 loads




   Number of warnings:  0
   Number of errors:    0
     




Design Errors/Warnings

   No errors or warnings present.



IO (PIO) Attributes

+---------------------+-----------+-----------+------------+
| IO Name             | Direction | Levelmode | IO         |
|                     |           |  IO_TYPE  | Register   |
+---------------------+-----------+-----------+------------+
| SoundWave_o         | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| Busy_o              | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| Reset               | INPUT     | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| Play_i              | INPUT     | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| Stop_i              | INPUT     | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+



Removed logic

Block i237 undriven or does not drive anything - clipped.
Signal Clock_enable_1 was merged into signal Play_i_c

Signal GND_net undriven or does not drive anything - clipped.
Signal VCC_net undriven or does not drive anything - clipped.
Signal DUT/StrobeGeneratorMilli/sub_6_add_2_1/S0 undriven or does not drive
     anything - clipped.
Signal DUT/StrobeGeneratorMilli/sub_6_add_2_1/CI undriven or does not drive
     anything - clipped.
Signal DUT/StrobeGeneratorMilli/sub_6_add_2_15/S1 undriven or does not drive
     anything - clipped.
Signal DUT/StrobeGeneratorMilli/sub_6_add_2_15/CO undriven or does not drive
     anything - clipped.
Signal DUT/sub_29_add_2_17/S1 undriven or does not drive anything - clipped.
Signal DUT/sub_29_add_2_17/CO undriven or does not drive anything - clipped.
Signal DUT/add_45_1/S0 undriven or does not drive anything - clipped.
Signal DUT/add_45_1/CI undriven or does not drive anything - clipped.
Signal DUT/sub_29_add_2_1/S0 undriven or does not drive anything - clipped.
Signal DUT/sub_29_add_2_1/CI undriven or does not drive anything - clipped.
Signal DUT/add_45_17/S1 undriven or does not drive anything - clipped.
Signal DUT/add_45_17/CO undriven or does not drive anything - clipped.
Block Play_i_I_0_1_lut_rep_3 was optimized away.
Block i1 was optimized away.

     

OSC Summary
-----------

OSC 1:                                     Pin/Node Value
  OSC Instance Name:                                OSCH_inst
  OSC Type:                                         OSCH
  STDBY Input:                                      NONE
  OSC Output:                              NODE     Clock
  OSC Nominal Frequency (MHz):                      14.00



ASIC Components
---------------

Instance Name: OSCH_inst
         Type: OSCH



GSR Usage
---------

GSR Component:
   The Global Set Reset (GSR) resource has been used to implement a global reset
        of the design. The reset signal used for GSR control is 'Reset_c'.
        

     GSR Property:
   The design components with GSR property set to ENABLED will respond to global
        set reset while the components with GSR property set to DISABLED will
        not.
        

     Components with synchronous local reset also reset by asynchronous GSR
----------------------------------------------------------------------


     These components have the GSR property set to ENABLED and the local reset
     is synchronous. The components will respond to the synchronous local reset
     and to the unrelated asynchronous reset signal 'Reset_c' via the GSR
     component.

     Type and number of components of the type: 
   Register = 42 

     Type and instance name of component: 
   Register : DUT/HalfPeriodTimer_i0
   Register : DUT/DurationTimer_i0
   Register : DUT/Signal_46
   Register : DUT/HalfPeriodTimer_i1
   Register : DUT/HalfPeriodTimer_i3
   Register : DUT/HalfPeriodTimer_i4
   Register : DUT/HalfPeriodTimer_i7
   Register : DUT/HalfPeriodTimer_i8
   Register : DUT/HalfPeriodTimer_i9
   Register : DUT/HalfPeriodTimer_i10
   Register : DUT/HalfPeriodTimer_i11
   Register : DUT/HalfPeriodTimer_i12
   Register : DUT/HalfPeriodTimer_i13
   Register : DUT/HalfPeriodTimer_i14
   Register : DUT/HalfPeriodTimer_i15
   Register : DUT/DurationTimer_i1
   Register : DUT/DurationTimer_i2
   Register : DUT/DurationTimer_i4
   Register : DUT/DurationTimer_i10
   Register : DUT/DurationTimer_i11
   Register : DUT/DurationTimer_i12
   Register : DUT/DurationTimer_i13
   Register : DUT/DurationTimer_i14
   Register : DUT/DurationTimer_i15
   Register : DUT/StrobeGeneratorMilli/Counter_i0
   Register : DUT/StrobeGeneratorMilli/Counter_i1
   Register : DUT/StrobeGeneratorMilli/Counter_i2
   Register : DUT/StrobeGeneratorMilli/Counter_i3
   Register : DUT/StrobeGeneratorMilli/Counter_i4
   Register : DUT/StrobeGeneratorMilli/Counter_i5
   Register : DUT/StrobeGeneratorMilli/Counter_i6
   Register : DUT/StrobeGeneratorMilli/Counter_i7
   Register : DUT/StrobeGeneratorMilli/Counter_i8
   Register : DUT/StrobeGeneratorMilli/Counter_i9
   Register : DUT/StrobeGeneratorMilli/Counter_i10
   Register : DUT/StrobeGeneratorMilli/Counter_i11
   Register : DUT/StrobeGeneratorMilli/Counter_i12
   Register : DUT/StrobeGeneratorMilli/Counter_i13
   Register : DUT/StrobeGeneratorMicro/Counter_i0
   Register : DUT/StrobeGeneratorMicro/Counter_i1
   Register : DUT/StrobeGeneratorMicro/Counter_i2
   Register : DUT/StrobeGeneratorMicro/Counter_i3



Run Time and Memory Usage
-------------------------

   Total CPU Time: 0 secs  

   Total REAL Time: 0 secs  
   Peak Memory Usage: 39 MB
        
























































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