Lattice Synthesis Timing Report -------------------------------------------------------------------------------- Lattice Synthesis Timing Report, Version Sat Sep 23 12:00:26 2023 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Design: top Constraint file: Report level: verbose report, limited to 3 items per constraint -------------------------------------------------------------------------------- ================================================================================ Constraint: create_clock -period 5.000000 -name clk0 [get_nets Clock] 3864 items scored, 3755 timing errors detected. -------------------------------------------------------------------------------- Error: The following path violates requirements by 6.236ns Logical Details: Cell type Pin type Cell name (clock net +/-) Source: FD1S3IX CK \DUT/DurationTimer_i2 (from Clock +) Destination: FD1S3AX D \DUT/DurationTimer_i9 (to Clock +) Delay: 11.090ns (40.7% logic, 59.3% route), 12 logic levels. Constraint Details: 11.090ns data_path \DUT/DurationTimer_i2 to \DUT/DurationTimer_i9 violates 5.000ns delay constraint less 0.146ns L_S requirement (totaling 4.854ns) by 6.236ns Path Details: \DUT/DurationTimer_i2 to \DUT/DurationTimer_i9 Name Fanout Delay (ns) Pins Resource(Cell.Net) L_CO --- 0.403 CK to Q \DUT/DurationTimer_i2 (from Clock) Route 2 e 1.002 \DUT/DurationTimer[2] LUT4 --- 0.448 A to Z \DUT/i6_2_lut_adj_4 Route 1 e 0.788 \DUT/n22_adj_143 LUT4 --- 0.448 C to Z \DUT/i14_4_lut Route 1 e 0.788 \DUT/n30 LUT4 --- 0.448 B to Z \DUT/i15_4_lut_adj_8 Route 25 e 1.537 Busy_o_c LUT4 --- 0.448 B to Z \DUT/i65_3_lut Route 1 e 0.788 \DUT/n116 A1_TO_FCO --- 0.752 D[2] to COUT \DUT/add_45_1 Route 1 e 0.020 \DUT/n262 FCI_TO_FCO --- 0.143 CIN to COUT \DUT/add_45_3 Route 1 e 0.020 \DUT/n263 FCI_TO_FCO --- 0.143 CIN to COUT \DUT/add_45_5 Route 1 e 0.020 \DUT/n264 FCI_TO_FCO --- 0.143 CIN to COUT \DUT/add_45_7 Route 1 e 0.020 \DUT/n265 FCI_TO_FCO --- 0.143 CIN to COUT \DUT/add_45_9 Route 1 e 0.020 \DUT/n266 FCI_TO_F --- 0.544 CIN to S[2] \DUT/add_45_11 Route 1 e 0.788 DurationTimer_15__N_55[9] LUT4 --- 0.448 B to Z i185_2_lut_2_lut Route 1 e 0.788 DurationTimer_15__N_5[9] -------- 11.090 (40.7% logic, 59.3% route), 12 logic levels. Error: The following path violates requirements by 6.236ns Logical Details: Cell type Pin type Cell name (clock net +/-) Source: FD1S3AX CK \DUT/DurationTimer_i7 (from Clock +) Destination: FD1S3AX D \DUT/DurationTimer_i9 (to Clock +) Delay: 11.090ns (40.7% logic, 59.3% route), 12 logic levels. Constraint Details: 11.090ns data_path \DUT/DurationTimer_i7 to \DUT/DurationTimer_i9 violates 5.000ns delay constraint less 0.146ns L_S requirement (totaling 4.854ns) by 6.236ns Path Details: \DUT/DurationTimer_i7 to \DUT/DurationTimer_i9 Name Fanout Delay (ns) Pins Resource(Cell.Net) L_CO --- 0.403 CK to Q \DUT/DurationTimer_i7 (from Clock) Route 2 e 1.002 \DUT/DurationTimer[7] LUT4 --- 0.448 B to Z \DUT/i6_2_lut_adj_4 Route 1 e 0.788 \DUT/n22_adj_143 LUT4 --- 0.448 C to Z \DUT/i14_4_lut Route 1 e 0.788 \DUT/n30 LUT4 --- 0.448 B to Z \DUT/i15_4_lut_adj_8 Route 25 e 1.537 Busy_o_c LUT4 --- 0.448 B to Z \DUT/i65_3_lut Route 1 e 0.788 \DUT/n116 A1_TO_FCO --- 0.752 D[2] to COUT \DUT/add_45_1 Route 1 e 0.020 \DUT/n262 FCI_TO_FCO --- 0.143 CIN to COUT \DUT/add_45_3 Route 1 e 0.020 \DUT/n263 FCI_TO_FCO --- 0.143 CIN to COUT \DUT/add_45_5 Route 1 e 0.020 \DUT/n264 FCI_TO_FCO --- 0.143 CIN to COUT \DUT/add_45_7 Route 1 e 0.020 \DUT/n265 FCI_TO_FCO --- 0.143 CIN to COUT \DUT/add_45_9 Route 1 e 0.020 \DUT/n266 FCI_TO_F --- 0.544 CIN to S[2] \DUT/add_45_11 Route 1 e 0.788 DurationTimer_15__N_55[9] LUT4 --- 0.448 B to Z i185_2_lut_2_lut Route 1 e 0.788 DurationTimer_15__N_5[9] -------- 11.090 (40.7% logic, 59.3% route), 12 logic levels. Error: The following path violates requirements by 6.236ns Logical Details: Cell type Pin type Cell name (clock net +/-) Source: FD1S3AX CK \DUT/DurationTimer_i9 (from Clock +) Destination: FD1S3AX D \DUT/DurationTimer_i9 (to Clock +) Delay: 11.090ns (40.7% logic, 59.3% route), 12 logic levels. Constraint Details: 11.090ns data_path \DUT/DurationTimer_i9 to \DUT/DurationTimer_i9 violates 5.000ns delay constraint less 0.146ns L_S requirement (totaling 4.854ns) by 6.236ns Path Details: \DUT/DurationTimer_i9 to \DUT/DurationTimer_i9 Name Fanout Delay (ns) Pins Resource(Cell.Net) L_CO --- 0.403 CK to Q \DUT/DurationTimer_i9 (from Clock) Route 2 e 1.002 \DUT/DurationTimer[9] LUT4 --- 0.448 B to Z \DUT/i12_4_lut_adj_3 Route 1 e 0.788 \DUT/n28_adj_142 LUT4 --- 0.448 B to Z \DUT/i14_4_lut Route 1 e 0.788 \DUT/n30 LUT4 --- 0.448 B to Z \DUT/i15_4_lut_adj_8 Route 25 e 1.537 Busy_o_c LUT4 --- 0.448 B to Z \DUT/i65_3_lut Route 1 e 0.788 \DUT/n116 A1_TO_FCO --- 0.752 D[2] to COUT \DUT/add_45_1 Route 1 e 0.020 \DUT/n262 FCI_TO_FCO --- 0.143 CIN to COUT \DUT/add_45_3 Route 1 e 0.020 \DUT/n263 FCI_TO_FCO --- 0.143 CIN to COUT \DUT/add_45_5 Route 1 e 0.020 \DUT/n264 FCI_TO_FCO --- 0.143 CIN to COUT \DUT/add_45_7 Route 1 e 0.020 \DUT/n265 FCI_TO_FCO --- 0.143 CIN to COUT \DUT/add_45_9 Route 1 e 0.020 \DUT/n266 FCI_TO_F --- 0.544 CIN to S[2] \DUT/add_45_11 Route 1 e 0.788 DurationTimer_15__N_55[9] LUT4 --- 0.448 B to Z i185_2_lut_2_lut Route 1 e 0.788 DurationTimer_15__N_5[9] -------- 11.090 (40.7% logic, 59.3% route), 12 logic levels. Warning: 11.236 ns is the maximum delay for this constraint. Timing Report Summary -------------- -------------------------------------------------------------------------------- Constraint | Constraint| Actual|Levels -------------------------------------------------------------------------------- | | | create_clock -period 5.000000 -name | | | clk0 [get_nets Clock] | 5.000 ns| 11.236 ns| 12 * | | | -------------------------------------------------------------------------------- 1 constraints not met. -------------------------------------------------------------------------------- Critical Nets | Loads| Errors| % of total -------------------------------------------------------------------------------- Busy_o_c | 25| 3136| 83.52% | | | \DUT/n30 | 1| 1568| 41.76% | | | \DUT/n265 | 1| 1212| 32.28% | | | \DUT/n266 | 1| 1156| 30.79% | | | \DUT/n264 | 1| 1126| 29.99% | | | \DUT/n267 | 1| 978| 26.05% | | | \DUT/n263 | 1| 890| 23.70% | | | \DUT/n26 | 1| 784| 20.88% | | | \DUT/n28_adj_142 | 1| 784| 20.88% | | | \DUT/n268 | 1| 686| 18.27% | | | \DUT/n262 | 1| 512| 13.64% | | | \DUT/n17 | 1| 392| 10.44% | | | \DUT/n18_adj_144 | 1| 392| 10.44% | | | \DUT/n22_adj_143 | 1| 392| 10.44% | | | n37 | 14| 392| 10.44% | | | -------------------------------------------------------------------------------- Timing summary: --------------- Timing errors: 3755 Score: 9665368 Constraints cover 4242 paths, 179 nets, and 382 connections (86.0% coverage) Peak memory: 63827968 bytes, TRCE: 3162112 bytes, DLYMAN: 0 bytes CPU_TIME_REPORT: 0 secs