Synthesis and Ngdbuild  Report
synthesis:  version Diamond (64-bit) 3.12.1.454

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
Sat Sep 23 12:00:25 2023


Command Line:  synthesis -f Kurs16_impl1_lattice.synproj -gui 

Synthesis options:
The -a option is MachXO2.
The -s option is 5.
The -t option is TQFP100.
The -d option is LCMXO2-1200HC.
Using package TQFP100.
Using performance grade 5.
                                                          

##########################################################

### Lattice Family : MachXO2

### Device  : LCMXO2-1200HC

### Package : TQFP100

### Speed   : 5

##########################################################

                                                          

INFO - synthesis: User-Selected Strategy Settings
Optimization goal = Balanced
Top-level module name = top.
Target frequency = 200.000000 MHz.
Maximum fanout = 1000.
Timing path count = 3
BRAM utilization = 100.000000 %
DSP usage = true
DSP utilization = 100.000000 %
fsm_encoding_style = auto
resolve_mixed_drivers = 0
fix_gated_clocks = 1

Mux style = Auto
Use Carry Chain = true
carry_chain_length = 0
Loop Limit = 1950.
Use IO Insertion = TRUE
Use IO Reg = AUTO

Resource Sharing = TRUE
Propagate Constants = TRUE
Remove Duplicate Registers = TRUE
force_gsr = auto
ROM style = auto
RAM style = auto
The -comp option is FALSE.
The -syn option is FALSE.
-p C:/Lattice/Kurs16 (searchpath added)
-p C:/lscc/diamond/3.12/ispfpga/xo2c00/data (searchpath added)
-p C:/Lattice/Kurs16/impl1 (searchpath added)
-p C:/Lattice/Kurs16 (searchpath added)
Verilog design file = C:/Lattice/Kurs16/impl1/source/sound_generator.v
Verilog design file = C:/Lattice/Kurs16/impl1/source/strobe_generator.v
Verilog design file = C:/Lattice/Kurs16/impl1/source/top.v
NGD file = Kurs16_impl1.ngd
-sdc option: SDC file input not used.
-lpf option: Output file option is ON.
Hardtimer checking is enabled (default). The -dt option is not used.
The -r option is OFF. [ Remove LOC Properties is OFF. ]
Technology check ok...

Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
Compile design.
Compile Design Begin
Analyzing Verilog file c:/lattice/kurs16/impl1/source/sound_generator.v. VERI-1482
Analyzing Verilog file c:/lattice/kurs16/impl1/source/strobe_generator.v. VERI-1482
Analyzing Verilog file c:/lattice/kurs16/impl1/source/top.v. VERI-1482
Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
Top module name (Verilog): top
INFO - synthesis: c:/lattice/kurs16/impl1/source/top.v(4): compiling module top. VERI-1018
INFO - synthesis: C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1793): compiling module OSCH(NOM_FREQ="14.00"). VERI-1018
INFO - synthesis: c:/lattice/kurs16/impl1/source/sound_generator.v(4): compiling module SoundGenerator(CLOCK_HZ=14000000). VERI-1018
INFO - synthesis: c:/lattice/kurs16/impl1/source/strobe_generator.v(4): compiling module StrobeGenerator(CLOCK_HZ=14000000,PERIOD_US=1000). VERI-1018
INFO - synthesis: c:/lattice/kurs16/impl1/source/strobe_generator.v(4): compiling module StrobeGenerator(CLOCK_HZ=14000000,PERIOD_US=1). VERI-1018
WARNING - synthesis: c:/lattice/kurs16/impl1/source/sound_generator.v(115): system task display ignored for synthesis. VERI-1142
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00a/data/xo2alib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
Loading device for application map from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status:                     Final          Version 1.44.
Top-level module name = top.



WARNING - synthesis: Bit 15 of Register \DUT/HalfPeriodCopy is stuck at Zero
WARNING - synthesis: Bit 14 of Register \DUT/HalfPeriodCopy is stuck at Zero
WARNING - synthesis: Bit 13 of Register \DUT/HalfPeriodCopy is stuck at Zero
WARNING - synthesis: Bit 12 of Register \DUT/HalfPeriodCopy is stuck at Zero
WARNING - synthesis: Bit 11 of Register \DUT/HalfPeriodCopy is stuck at Zero
WARNING - synthesis: Bit 10 of Register \DUT/HalfPeriodCopy is stuck at Zero
WARNING - synthesis: Bit 9 of Register \DUT/HalfPeriodCopy is stuck at Zero
WARNING - synthesis: Bit 8 of Register \DUT/HalfPeriodCopy is stuck at Zero
WARNING - synthesis: Bit 7 of Register \DUT/HalfPeriodCopy is stuck at Zero
WARNING - synthesis: Bit 4 of Register \DUT/HalfPeriodCopy is stuck at Zero
WARNING - synthesis: Bit 3 of Register \DUT/HalfPeriodCopy is stuck at Zero
WARNING - synthesis: Bit 1 of Register \DUT/HalfPeriodCopy is stuck at Zero
WARNING - synthesis: Bit 0 of Register \DUT/HalfPeriodCopy is stuck at Zero
GSR instance connected to net Reset_c.
Applying 200.000000 MHz constraint to all clocks

WARNING - synthesis: No user .sdc file.
Results of NGD DRC are available in top_drc.log.
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00a/data/xo2alib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
All blocks are expanded and NGD expansion is successful.
Writing NGD file Kurs16_impl1.ngd.

################### Begin Area Report (top)######################
Number of register bits => 54 of 1520 (3 % )
CCU2D => 26
FD1P3AX => 6
FD1P3IX => 14
FD1S3AX => 6
FD1S3IX => 15
FD1S3JX => 13
GSR => 1
IB => 3
LUT4 => 58
OB => 2
OSCH => 1
################### End Area Report ##################

################### Begin BlackBox Report ######################
TSALL => 1
################### End BlackBox Report ##################

################### Begin Clock Report ######################
Clock Nets
Number of Clocks: 1
  Net : Clock, loads : 54
Clock Enable Nets
Number of Clock Enables: 5
Top 5 highest fanout Clock Enables:
  Net : DUT/Clock_enable_20, loads : 13
  Net : DUT/Clock_enable_4, loads : 1
  Net : Clock_enable_11, loads : 1
  Net : Clock_enable_1, loads : 1
  Net : Clock_enable_6, loads : 1
Highest fanout non-clock nets
Top 10 highest fanout non-clock nets:
  Net : DUT/Busy_o_c, loads : 24
  Net : Clock_enable_1, loads : 24
  Net : Play_i_c, loads : 16
  Net : Stop_i_c, loads : 16
  Net : DUT/n31, loads : 16
  Net : DUT/StrobeGeneratorMilli/TickMilli, loads : 16
  Net : n37, loads : 14
  Net : DUT/Clock_enable_20, loads : 13
  Net : DUT/HalfPeriodCopy_6, loads : 5
  Net : DUT/StrobeGeneratorMicro/Counter_0, loads : 5
################### End Clock Report ##################

Timing Report Summary
--------------
--------------------------------------------------------------------------------
Constraint                              |   Constraint|       Actual|Levels
--------------------------------------------------------------------------------
                                        |             |             |
create_clock -period 5.000000 -name     |             |             |
clk0 [get_nets Clock]                   |  200.000 MHz|   89.000 MHz|    12 *
                                        |             |             |
--------------------------------------------------------------------------------


1 constraints not met.


Peak Memory Usage: 60.875  MB

--------------------------------------------------------------
Elapsed CPU time for LSE flow : 0.156  secs
--------------------------------------------------------------