Setting log file to 'C:/Lattice/Kurs16/impl1/hdla_gen_hierarchy.html'.
Starting: parse design source files
(VERI-1482) Analyzing Verilog file 'C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v'
(VERI-1482) Analyzing Verilog file 'C:/Lattice/Kurs16/impl1/source/sound_generator.v'
(VERI-1482) Analyzing Verilog file 'C:/Lattice/Kurs16/impl1/source/strobe_generator.v'
(VERI-1482) Analyzing Verilog file 'C:/Lattice/Kurs16/impl1/source/top.v'
INFO - C:/Lattice/Kurs16/impl1/source/top.v(4,8-4,11) (VERI-1018) compiling module 'top'
INFO - C:/Lattice/Kurs16/impl1/source/top.v(4,1-39,10) (VERI-9000) elaborating module 'top'
INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1793,1-1798,10) (VERI-9000) elaborating module 'OSCH_uniq_1'
INFO - C:/Lattice/Kurs16/impl1/source/sound_generator.v(4,1-119,10) (VERI-9000) elaborating module 'SoundGenerator_uniq_1'
INFO - C:/Lattice/Kurs16/impl1/source/strobe_generator.v(4,1-41,10) (VERI-9000) elaborating module 'StrobeGenerator_uniq_1'
INFO - C:/Lattice/Kurs16/impl1/source/strobe_generator.v(4,1-41,10) (VERI-9000) elaborating module 'StrobeGenerator_uniq_2'
Done: design load finished with (0) errors, and (0) warnings