Lattice Synthesis Timing Report
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Lattice Synthesis Timing Report, Version
Tue Dec 24 11:11:48 2024
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2023 Lattice Semiconductor Corporation, All rights reserved.
Report Information
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Design: top
Constraint file:
Report level: verbose report, limited to 3 items per constraint
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================================================================================
Constraint: create_clock -period 5.000000 -name clk0 [get_nets Clock_c]
3319 items scored, 3319 timing errors detected.
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Error: The following path violates requirements by 6.976ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FD1P3AX CK \UartRx_Inst/Data_o_i0_i7 (from Clock_c +)
Destination: FD1P3AX D \Memory_inst/CursorY_i0 (to Clock_c +)
Delay: 11.830ns (26.1% logic, 73.9% route), 7 logic levels.
Constraint Details:
11.830ns data_path \UartRx_Inst/Data_o_i0_i7 to \Memory_inst/CursorY_i0 violates
5.000ns delay constraint less
0.146ns L_S requirement (totaling 4.854ns) by 6.976ns
Path Details: \UartRx_Inst/Data_o_i0_i7 to \Memory_inst/CursorY_i0
Name Fanout Delay (ns) Pins Resource(Cell.Net)
L_CO --- 0.403 CK to Q \UartRx_Inst/Data_o_i0_i7 (from Clock_c)
Route 47 e 1.769 DataFromUART[7]
LUT4 --- 0.448 D to Z \Memory_inst/i2_3_lut_4_lut
Route 2 e 0.954 n4278
LUT4 --- 0.448 D to Z \DisplayMultiplex_inst/i3_4_lut
Route 10 e 1.340 n15
LUT4 --- 0.448 B to Z \Memory_inst/i2_4_lut
Route 42 e 1.716 \Memory_inst/n2719
LUT4 --- 0.448 A to Z \Memory_inst/select_35_Select_0_i6_2_lut
Route 12 e 1.384 \Memory_inst/n1317
LUT4 --- 0.448 C to Z \Memory_inst/i1_4_lut_4_lut_adj_57
Route 1 e 0.788 \Memory_inst/n4_adj_533
LUT4 --- 0.448 B to Z \Memory_inst/CursorY_4__I_1_i1_4_lut_4_lut
Route 1 e 0.788 \Memory_inst/CursorY_4__N_143[0]
--------
11.830 (26.1% logic, 73.9% route), 7 logic levels.
Error: The following path violates requirements by 6.976ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FD1P3AX CK \UartRx_Inst/Data_o_i0_i7 (from Clock_c +)
Destination: FD1P3AX D \Memory_inst/CursorY_i4 (to Clock_c +)
Delay: 11.830ns (26.1% logic, 73.9% route), 7 logic levels.
Constraint Details:
11.830ns data_path \UartRx_Inst/Data_o_i0_i7 to \Memory_inst/CursorY_i4 violates
5.000ns delay constraint less
0.146ns L_S requirement (totaling 4.854ns) by 6.976ns
Path Details: \UartRx_Inst/Data_o_i0_i7 to \Memory_inst/CursorY_i4
Name Fanout Delay (ns) Pins Resource(Cell.Net)
L_CO --- 0.403 CK to Q \UartRx_Inst/Data_o_i0_i7 (from Clock_c)
Route 47 e 1.769 DataFromUART[7]
LUT4 --- 0.448 D to Z \Memory_inst/i2_3_lut_4_lut
Route 2 e 0.954 n4278
LUT4 --- 0.448 D to Z \DisplayMultiplex_inst/i3_4_lut
Route 10 e 1.340 n15
LUT4 --- 0.448 B to Z \Memory_inst/i2_4_lut
Route 42 e 1.716 \Memory_inst/n2719
LUT4 --- 0.448 A to Z \Memory_inst/select_35_Select_0_i6_2_lut
Route 12 e 1.384 \Memory_inst/n1317
LUT4 --- 0.448 D to Z \Memory_inst/i1_4_lut
Route 1 e 0.788 \Memory_inst/n4_adj_540
LUT4 --- 0.448 D to Z \Memory_inst/CursorY_4__I_1_i5_4_lut
Route 1 e 0.788 \Memory_inst/CursorY_4__N_143[4]
--------
11.830 (26.1% logic, 73.9% route), 7 logic levels.
Error: The following path violates requirements by 6.976ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FD1P3AX CK \UartRx_Inst/Data_o_i0_i7 (from Clock_c +)
Destination: FD1P3AX D \Memory_inst/CursorY_i3 (to Clock_c +)
Delay: 11.830ns (26.1% logic, 73.9% route), 7 logic levels.
Constraint Details:
11.830ns data_path \UartRx_Inst/Data_o_i0_i7 to \Memory_inst/CursorY_i3 violates
5.000ns delay constraint less
0.146ns L_S requirement (totaling 4.854ns) by 6.976ns
Path Details: \UartRx_Inst/Data_o_i0_i7 to \Memory_inst/CursorY_i3
Name Fanout Delay (ns) Pins Resource(Cell.Net)
L_CO --- 0.403 CK to Q \UartRx_Inst/Data_o_i0_i7 (from Clock_c)
Route 47 e 1.769 DataFromUART[7]
LUT4 --- 0.448 D to Z \Memory_inst/i2_3_lut_4_lut
Route 2 e 0.954 n4278
LUT4 --- 0.448 D to Z \DisplayMultiplex_inst/i3_4_lut
Route 10 e 1.340 n15
LUT4 --- 0.448 B to Z \Memory_inst/i2_4_lut
Route 42 e 1.716 \Memory_inst/n2719
LUT4 --- 0.448 A to Z \Memory_inst/select_35_Select_0_i6_2_lut
Route 12 e 1.384 \Memory_inst/n1317
LUT4 --- 0.448 D to Z \Memory_inst/i1_4_lut_adj_44
Route 1 e 0.788 \Memory_inst/n4_adj_542
LUT4 --- 0.448 D to Z \Memory_inst/CursorY_4__I_1_i4_4_lut
Route 1 e 0.788 \Memory_inst/CursorY_4__N_143[3]
--------
11.830 (26.1% logic, 73.9% route), 7 logic levels.
Warning: 11.976 ns is the maximum delay for this constraint.
Timing Report Summary
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Constraint | Constraint| Actual|Levels
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| | |
create_clock -period 5.000000 -name | | |
clk0 [get_nets Clock_c] | 5.000 ns| 11.976 ns| 7 *
| | |
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1 constraints not met.
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Critical Nets | Loads| Errors| % of total
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\Memory_inst/n2719 | 42| 1296| 39.05%
| | |
n15 | 10| 576| 17.35%
| | |
n4278 | 2| 556| 16.75%
| | |
\Memory_inst/n1846 | 5| 534| 16.09%
| | |
\Memory_inst/n3750 | 1| 456| 13.74%
| | |
\Memory_inst/n3749 | 1| 425| 12.81%
| | |
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Timing summary:
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Timing errors: 3319 Score: 9942939
Constraints cover 5453 paths, 639 nets, and 1977 connections (91.9% coverage)
Peak memory: 94547968 bytes, TRCE: 0 bytes, DLYMAN: 0 bytes
CPU_TIME_REPORT: 0 secs