Synthesis and Ngdbuild Report
synthesis: version Diamond (64-bit) 3.13.0.56.2
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2023 Lattice Semiconductor Corporation, All rights reserved.
Tue Dec 24 11:11:47 2024
Command Line: synthesis -f Kurs29_impl1_lattice.synproj -gui -msgset C:/Lattice/Kurs29/promote.xml
Synthesis options:
The -a option is MachXO2.
The -s option is 5.
The -t option is TQFP100.
The -d option is LCMXO2-1200HC.
Using package TQFP100.
Using performance grade 5.
##########################################################
### Lattice Family : MachXO2
### Device : LCMXO2-1200HC
### Package : TQFP100
### Speed : 5
##########################################################
INFO - synthesis: User-Selected Strategy Settings
Optimization goal = Balanced
Top-level module name = top.
Target frequency = 200.000000 MHz.
Maximum fanout = 1000.
Timing path count = 3
BRAM utilization = 100.000000 %
DSP usage = true
DSP utilization = 100.000000 %
fsm_encoding_style = auto
resolve_mixed_drivers = 0
fix_gated_clocks = 1
Mux style = Auto
Use Carry Chain = true
carry_chain_length = 0
Loop Limit = 1950.
Use IO Insertion = TRUE
Use IO Reg = AUTO
Resource Sharing = TRUE
Propagate Constants = TRUE
Remove Duplicate Registers = TRUE
force_gsr = auto
ROM style = auto
RAM style = auto
The -comp option is FALSE.
The -syn option is FALSE.
-p C:/Lattice/Kurs29 (searchpath added)
-p C:/lscc/diamond/3.13/ispfpga/xo2c00/data (searchpath added)
-p C:/Lattice/Kurs29/impl1 (searchpath added)
-p C:/Lattice/Kurs29 (searchpath added)
Verilog design file = C:/Lattice/Kurs29/impl1/source/top.v
Verilog design file = C:/Lattice/Kurs29/impl1/source/vga.v
Verilog design file = C:/Lattice/Kurs29/impl1/source/uart_rx.v
Verilog design file = C:/Lattice/Kurs29/impl1/source/synchronizer.v
Verilog design file = C:/Lattice/Kurs29/impl1/source/edge_detector.v
Verilog design file = C:/Lattice/Kurs29/impl1/source/strobe_generator_ticks.v
Verilog design file = C:/Lattice/Kurs29/impl1/source/display_multiplex.v
Verilog design file = C:/Lattice/Kurs29/impl1/source/decoder_7seg.v
Verilog design file = C:/Lattice/Kurs29/impl1/source/strobe_generator.v
Verilog design file = C:/Lattice/Kurs29/impl1/source/memory.v
Verilog design file = C:/Lattice/Kurs29/impl1/source/ram_pdp.v
Verilog design file = C:/Lattice/Kurs29/impl1/source/rom.v
NGD file = Kurs29_impl1.ngd
-sdc option: SDC file input not used.
-lpf option: Output file option is ON.
Hardtimer checking is enabled (default). The -dt option is not used.
The -r option is OFF. [ Remove LOC Properties is OFF. ]
Technology check ok...
Analyzing Verilog file C:/lscc/diamond/3.13/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
Compile design.
Compile Design Begin
Analyzing Verilog file c:/lattice/kurs29/impl1/source/top.v. VERI-1482
Analyzing Verilog file c:/lattice/kurs29/impl1/source/vga.v. VERI-1482
Analyzing Verilog file c:/lattice/kurs29/impl1/source/uart_rx.v. VERI-1482
Analyzing Verilog file c:/lattice/kurs29/impl1/source/synchronizer.v. VERI-1482
Analyzing Verilog file c:/lattice/kurs29/impl1/source/edge_detector.v. VERI-1482
Analyzing Verilog file c:/lattice/kurs29/impl1/source/strobe_generator_ticks.v. VERI-1482
Analyzing Verilog file c:/lattice/kurs29/impl1/source/display_multiplex.v. VERI-1482
Analyzing Verilog file c:/lattice/kurs29/impl1/source/decoder_7seg.v. VERI-1482
Analyzing Verilog file c:/lattice/kurs29/impl1/source/strobe_generator.v. VERI-1482
Analyzing Verilog file c:/lattice/kurs29/impl1/source/memory.v. VERI-1482
WARNING - synthesis: c:/lattice/kurs29/impl1/source/memory.v(160): identifier DataFromImageRAM is used before its declaration. VERI-1875
WARNING - synthesis: c:/lattice/kurs29/impl1/source/memory.v(170): identifier DataFromFontROM is used before its declaration. VERI-1875
WARNING - synthesis: c:/lattice/kurs29/impl1/source/memory.v(171): identifier DataFromImageRAM is used before its declaration. VERI-1875
WARNING - synthesis: c:/lattice/kurs29/impl1/source/memory.v(172): identifier DataFromImageRAM is used before its declaration. VERI-1875
Analyzing Verilog file c:/lattice/kurs29/impl1/source/ram_pdp.v. VERI-1482
Analyzing Verilog file c:/lattice/kurs29/impl1/source/rom.v. VERI-1482
Analyzing Verilog file C:/lscc/diamond/3.13/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
Top module name (Verilog): top
INFO - synthesis: c:/lattice/kurs29/impl1/source/top.v(4): compiling module top. VERI-1018
INFO - synthesis: c:/lattice/kurs29/impl1/source/uart_rx.v(4): compiling module UartRx(CLOCK_HZ=25000000). VERI-1018
INFO - synthesis: c:/lattice/kurs29/impl1/source/synchronizer.v(4): compiling module Synchronizer. VERI-1018
INFO - synthesis: c:/lattice/kurs29/impl1/source/edge_detector.v(4): compiling module EdgeDetector. VERI-1018
INFO - synthesis: c:/lattice/kurs29/impl1/source/strobe_generator_ticks.v(4): compiling module StrobeGeneratorTicks(TICKS=108). VERI-1018
INFO - synthesis: c:/lattice/kurs29/impl1/source/memory.v(5): compiling module Memory. VERI-1018
INFO - synthesis: c:/lattice/kurs29/impl1/source/ram_pdp.v(4): compiling module PseudoDualPortRAM(ADDRESS_WIDTH=10,MEMORY_DEPTH=1024). VERI-1018
INFO - synthesis: c:/lattice/kurs29/impl1/source/ram_pdp.v(4): compiling module PseudoDualPortRAM(ADDRESS_WIDTH=10,MEMORY_DEPTH=704). VERI-1018
INFO - synthesis: c:/lattice/kurs29/impl1/source/rom.v(4): compiling module ROM(ADDRESS_WIDTH=11,MEMORY_DEPTH=2048,MEMORY_FILE="font_0_127.mem"). VERI-1018
WARNING - synthesis: c:/lattice/kurs29/impl1/source/rom.v(18): net Memory does not have a driver. VDB-1002
INFO - synthesis: c:/lattice/kurs29/impl1/source/vga.v(4): compiling module VGA. VERI-1018
INFO - synthesis: c:/lattice/kurs29/impl1/source/display_multiplex.v(4): compiling module DisplayMultiplex(CLOCK_HZ=25000000). VERI-1018
INFO - synthesis: c:/lattice/kurs29/impl1/source/strobe_generator.v(4): compiling module StrobeGenerator(CLOCK_HZ=25000000,PERIOD_US=1000). VERI-1018
INFO - synthesis: c:/lattice/kurs29/impl1/source/decoder_7seg.v(4): compiling module Decoder7seg. VERI-1018
Loading NGL library 'C:/lscc/diamond/3.13/ispfpga/xo2c00a/data/xo2alib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.13/ispfpga/xo2c00/data/xo2clib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.13/ispfpga/mg5g00/data/mg5glib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.13/ispfpga/or5g00/data/orc5glib.ngl'...
Loading device for application map from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.13/ispfpga.
Package Status: Final Version 1.44.
Top-level module name = top.
WARNING - synthesis: c:/lattice/kurs29/impl1/source/rom.v(18): ram Memory_original_ramnet has no write-port on it. VDB-1038
######## Found 5 RTL RAMs in the design.
######## Mapping RTL RAM \Memory_inst/ImageRAM_0/Memory to 1 EBR blocks in PSEUDO_DUAL_PORT Mode
######## Mapping RTL RAM \Memory_inst/ImageRAM_1/Memory to 1 EBR blocks in PSEUDO_DUAL_PORT Mode
######## Mapping RTL RAM \Memory_inst/ImageRAM_2/Memory to 1 EBR blocks in PSEUDO_DUAL_PORT Mode
######## Mapping RTL RAM \Memory_inst/ImageRAM_3/Memory to 1 EBR blocks in PSEUDO_DUAL_PORT Mode
######## Mapping RTL RAM \Memory_inst/ImageRAM_4/Memory to 1 EBR blocks in PSEUDO_DUAL_PORT Mode
GSR instance connected to net Reset_c.
Applying 200.000000 MHz constraint to all clocks
WARNING - synthesis: No user .sdc file.
Results of NGD DRC are available in top_drc.log.
Loading NGL library 'C:/lscc/diamond/3.13/ispfpga/xo2c00a/data/xo2alib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.13/ispfpga/xo2c00/data/xo2clib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.13/ispfpga/mg5g00/data/mg5glib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.13/ispfpga/or5g00/data/orc5glib.ngl'...
All blocks are expanded and NGD expansion is successful.
Writing NGD file Kurs29_impl1.ngd.
################### Begin Area Report (top)######################
Number of register bits => 168 of 1520 (11 % )
CCU2D => 29
DP8KC => 5
FD1P3AX => 89
FD1P3AY => 6
FD1P3IX => 29
FD1S3AX => 6
FD1S3IX => 22
FD1S3JX => 16
GSR => 1
IB => 3
L6MUX21 => 1
LUT4 => 345
OB => 21
PFUMX => 45
SP8KC => 2
################### End Area Report ##################
################### Begin BlackBox Report ######################
TSALL => 1
################### End BlackBox Report ##################
################### Begin Clock Report ######################
Clock Nets
Number of Clocks: 1
Net : Clock_c, loads : 180
Clock Enable Nets
Number of Clock Enables: 25
Top 10 highest fanout Clock Enables:
Net : Memory_inst/WriteRequest_N_336, loads : 22
Net : VGA_inst/Clock_c_enable_55, loads : 21
Net : Memory_inst/Clock_c_enable_89, loads : 17
Net : Memory_inst/Clock_c_enable_74, loads : 13
Net : Memory_inst/Clock_c_enable_84, loads : 11
Net : UartRx_Inst/Clock_c_enable_30, loads : 8
Net : UartRx_Inst/Clock_c_enable_62, loads : 8
Net : Memory_inst/Clock_c_enable_23, loads : 7
Net : Memory_inst/Clock_c_enable_17, loads : 5
Net : UartRx_Inst/Busy_N_39, loads : 4
Highest fanout non-clock nets
Top 10 highest fanout non-clock nets:
Net : UartRx_Inst/n5222, loads : 49
Net : UartRx_Inst/DataFromUART_7, loads : 46
Net : Memory_inst/n2719, loads : 42
Net : Memory_inst/CursorY_3, loads : 39
Net : Memory_inst/CursorY_4, loads : 39
Net : Memory_inst/CursorY_2, loads : 39
Net : Memory_inst/CursorY_1, loads : 26
Net : Memory_inst/CursorY_0, loads : 26
Net : Memory_inst/WriteRequest_N_336, loads : 22
Net : VGA_inst/Clock_c_enable_55, loads : 21
################### End Clock Report ##################
Timing Report Summary
--------------
--------------------------------------------------------------------------------
Constraint | Constraint| Actual|Levels
--------------------------------------------------------------------------------
| | |
create_clock -period 5.000000 -name | | |
clk0 [get_nets Clock_c] | 200.000 MHz| 83.500 MHz| 7 *
| | |
--------------------------------------------------------------------------------
1 constraints not met.
Peak Memory Usage: 90.168 MB
--------------------------------------------------------------
Elapsed CPU time for LSE flow : 1.375 secs
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