Setting log file to 'C:/Lattice/Kurs29/impl1/hdla_gen_hierarchy.html'.
Starting: parse design source files
(VERI-1482) Analyzing Verilog file 'C:/lscc/diamond/3.13/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v'
(VERI-1482) Analyzing Verilog file 'C:/Lattice/Kurs29/impl1/source/top.v'
(VERI-1482) Analyzing Verilog file 'C:/Lattice/Kurs29/impl1/source/vga.v'
(VERI-1482) Analyzing Verilog file 'C:/Lattice/Kurs29/impl1/source/uart_rx.v'
(VERI-1482) Analyzing Verilog file 'C:/Lattice/Kurs29/impl1/source/synchronizer.v'
(VERI-1482) Analyzing Verilog file 'C:/Lattice/Kurs29/impl1/source/edge_detector.v'
(VERI-1482) Analyzing Verilog file 'C:/Lattice/Kurs29/impl1/source/strobe_generator_ticks.v'
(VERI-1482) Analyzing Verilog file 'C:/Lattice/Kurs29/impl1/source/display_multiplex.v'
(VERI-1482) Analyzing Verilog file 'C:/Lattice/Kurs29/impl1/source/decoder_7seg.v'
(VERI-1482) Analyzing Verilog file 'C:/Lattice/Kurs29/impl1/source/strobe_generator.v'
(VERI-1482) Analyzing Verilog file 'C:/Lattice/Kurs29/impl1/source/memory.v'
WARNING - C:/Lattice/Kurs29/impl1/source/memory.v(160,21-160,37) (VERI-1875) identifier 'DataFromImageRAM' is used before its declaration
WARNING - C:/Lattice/Kurs29/impl1/source/memory.v(170,26-170,41) (VERI-1875) identifier 'DataFromFontROM' is used before its declaration
WARNING - C:/Lattice/Kurs29/impl1/source/memory.v(171,26-171,42) (VERI-1875) identifier 'DataFromImageRAM' is used before its declaration
WARNING - C:/Lattice/Kurs29/impl1/source/memory.v(172,26-172,42) (VERI-1875) identifier 'DataFromImageRAM' is used before its declaration
(VERI-1482) Analyzing Verilog file 'C:/Lattice/Kurs29/impl1/source/ram_pdp.v'
(VERI-1482) Analyzing Verilog file 'C:/Lattice/Kurs29/impl1/source/rom.v'
INFO - C:/Lattice/Kurs29/impl1/source/top.v(4,8-4,11) (VERI-1018) compiling module 'top'
INFO - C:/Lattice/Kurs29/impl1/source/top.v(4,1-106,10) (VERI-9000) elaborating module 'top'
INFO - C:/Lattice/Kurs29/impl1/source/uart_rx.v(4,1-91,10) (VERI-9000) elaborating module 'UartRx_uniq_1'
INFO - C:/Lattice/Kurs29/impl1/source/memory.v(5,1-294,10) (VERI-9000) elaborating module 'Memory_uniq_1'
INFO - C:/Lattice/Kurs29/impl1/source/vga.v(4,1-105,10) (VERI-9000) elaborating module 'VGA_uniq_1'
INFO - C:/Lattice/Kurs29/impl1/source/display_multiplex.v(4,1-77,10) (VERI-9000) elaborating module 'DisplayMultiplex_uniq_1'
INFO - C:/Lattice/Kurs29/impl1/source/synchronizer.v(4,1-28,10) (VERI-9000) elaborating module 'Synchronizer_uniq_1'
INFO - C:/Lattice/Kurs29/impl1/source/edge_detector.v(4,1-24,10) (VERI-9000) elaborating module 'EdgeDetector_uniq_1'
INFO - C:/Lattice/Kurs29/impl1/source/strobe_generator_ticks.v(4,1-34,10) (VERI-9000) elaborating module 'StrobeGeneratorTicks_uniq_1'
INFO - C:/Lattice/Kurs29/impl1/source/ram_pdp.v(4,1-51,10) (VERI-9000) elaborating module 'PseudoDualPortRAM_uniq_1'
INFO - C:/Lattice/Kurs29/impl1/source/ram_pdp.v(4,1-51,10) (VERI-9000) elaborating module 'PseudoDualPortRAM_uniq_2'
INFO - C:/Lattice/Kurs29/impl1/source/ram_pdp.v(4,1-51,10) (VERI-9000) elaborating module 'PseudoDualPortRAM_uniq_3'
INFO - C:/Lattice/Kurs29/impl1/source/ram_pdp.v(4,1-51,10) (VERI-9000) elaborating module 'PseudoDualPortRAM_uniq_4'
INFO - C:/Lattice/Kurs29/impl1/source/ram_pdp.v(4,1-51,10) (VERI-9000) elaborating module 'PseudoDualPortRAM_uniq_5'
INFO - C:/Lattice/Kurs29/impl1/source/rom.v(4,1-39,10) (VERI-9000) elaborating module 'ROM_uniq_1'
INFO - C:/Lattice/Kurs29/impl1/source/strobe_generator.v(4,1-41,10) (VERI-9000) elaborating module 'StrobeGenerator_uniq_1'
INFO - C:/Lattice/Kurs29/impl1/source/decoder_7seg.v(4,1-42,10) (VERI-9000) elaborating module 'Decoder7seg_uniq_1'
Done: design load finished with (0) errors, and (4) warnings