Place & Route TRACE Report
Loading design for application trce from file kurs29_impl1.ncd.
Design name: top
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-1200HC
Package: TQFP100
Performance: 5
Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.13/ispfpga.
Package Status: Final Version 1.44.
Performance Hardware Data Status: Final Version 34.4.
Setup and Hold Report
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Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.13.0.56.2
Thu Dec 19 19:34:40 2024
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2023 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 10 -gt -sethld -sp 5 -sphld m -o Kurs29_impl1.twr -gui -msgset C:/Lattice/Kurs29/promote.xml Kurs29_impl1.ncd Kurs29_impl1.prf
Design file: kurs29_impl1.ncd
Preference file: kurs29_impl1.prf
Device,speed: LCMXO2-1200HC,5
Report level: verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------
Preference Summary
FREQUENCY PORT "Clock" 25.000000 MHz (0 errors) 4096 items scored, 0 timing errors detected.
Report: 78.952MHz is the maximum frequency for this preference.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
BLOCK JTAG PATHS
--------------------------------------------------------------------------------
Derating parameters
-------------------
Voltage: 3.300 V
================================================================================
Preference: FREQUENCY PORT "Clock" 25.000000 MHz ;
4096 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 27.334ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Memory_inst/CursorY_i1 (from Clock_c +)
Destination: FF Data in Memory_inst/WriteAddress_i12 (to Clock_c +)
Delay: 12.516ns (30.1% logic, 69.9% route), 8 logic levels.
Constraint Details:
12.516ns physical path delay Memory_inst/SLICE_51 to Memory_inst/SLICE_78 meets
40.000ns delay constraint less
0.000ns skew and
0.150ns DIN_SET requirement (totaling 39.850ns) by 27.334ns
Physical Path Details:
Data path Memory_inst/SLICE_51 to Memory_inst/SLICE_78:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R8C8B.CLK to R8C8B.Q1 Memory_inst/SLICE_51 (from Clock_c)
ROUTE 26 3.573 R8C8B.Q1 to R7C5D.D0 Memory_inst/CursorY_1
CTOF_DEL --- 0.452 R7C5D.D0 to R7C5D.F0 Memory_inst/SLICE_206
ROUTE 7 1.799 R7C5D.F0 to R4C5B.D0 Memory_inst/n5207
CTOOFX_DEL --- 0.661 R4C5B.D0 to R4C5B.OFX0 Memory_inst/i4422/SLICE_137
ROUTE 1 0.882 R4C5B.OFX0 to R4C6C.B0 Memory_inst/n4977
CTOF_DEL --- 0.452 R4C6C.B0 to R4C6C.F0 Memory_inst/SLICE_186
ROUTE 1 1.622 R4C6C.F0 to R5C8C.B1 Memory_inst/n4315
C1TOFCO_DE --- 0.786 R5C8C.B1 to R5C8C.FCO Memory_inst/SLICE_26
ROUTE 1 0.000 R5C8C.FCO to R5C8D.FCI Memory_inst/n3750
FCITOFCO_D --- 0.146 R5C8D.FCI to R5C8D.FCO Memory_inst/SLICE_21
ROUTE 1 0.000 R5C8D.FCO to R5C9A.FCI Memory_inst/n3751
FCITOF0_DE --- 0.517 R5C9A.FCI to R5C9A.F0 Memory_inst/SLICE_24
ROUTE 1 0.872 R5C9A.F0 to R5C10C.M0 Memory_inst/WriteCharNum_11
MTOOFX_DEL --- 0.345 R5C10C.M0 to R5C10C.OFX0 Memory_inst/SLICE_78
ROUTE 1 0.000 R5C10C.OFX0 to R5C10C.DI0 Memory_inst/WriteAddress_12_N_115_12 (to Clock_c)
--------
12.516 (30.1% logic, 69.9% route), 8 logic levels.
Clock Skew Details:
Source Clock Path Clock to Memory_inst/SLICE_51:
Name Fanout Delay (ns) Site Resource
ROUTE 121 2.001 20.PADDI to R8C8B.CLK Clock_c
--------
2.001 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path Clock to Memory_inst/SLICE_78:
Name Fanout Delay (ns) Site Resource
ROUTE 121 2.001 20.PADDI to R5C10C.CLK Clock_c
--------
2.001 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 27.334ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Memory_inst/CursorY_i1 (from Clock_c +)
Destination: FF Data in Memory_inst/WriteAddress_i12 (to Clock_c +)
Delay: 12.516ns (30.1% logic, 69.9% route), 8 logic levels.
Constraint Details:
12.516ns physical path delay Memory_inst/SLICE_51 to Memory_inst/SLICE_78 meets
40.000ns delay constraint less
0.000ns skew and
0.150ns DIN_SET requirement (totaling 39.850ns) by 27.334ns
Physical Path Details:
Data path Memory_inst/SLICE_51 to Memory_inst/SLICE_78:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R8C8B.CLK to R8C8B.Q1 Memory_inst/SLICE_51 (from Clock_c)
ROUTE 26 3.573 R8C8B.Q1 to R7C5D.D0 Memory_inst/CursorY_1
CTOF_DEL --- 0.452 R7C5D.D0 to R7C5D.F0 Memory_inst/SLICE_206
ROUTE 7 1.799 R7C5D.F0 to R4C5B.D1 Memory_inst/n5207
CTOOFX_DEL --- 0.661 R4C5B.D1 to R4C5B.OFX0 Memory_inst/i4422/SLICE_137
ROUTE 1 0.882 R4C5B.OFX0 to R4C6C.B0 Memory_inst/n4977
CTOF_DEL --- 0.452 R4C6C.B0 to R4C6C.F0 Memory_inst/SLICE_186
ROUTE 1 1.622 R4C6C.F0 to R5C8C.B1 Memory_inst/n4315
C1TOFCO_DE --- 0.786 R5C8C.B1 to R5C8C.FCO Memory_inst/SLICE_26
ROUTE 1 0.000 R5C8C.FCO to R5C8D.FCI Memory_inst/n3750
FCITOFCO_D --- 0.146 R5C8D.FCI to R5C8D.FCO Memory_inst/SLICE_21
ROUTE 1 0.000 R5C8D.FCO to R5C9A.FCI Memory_inst/n3751
FCITOF0_DE --- 0.517 R5C9A.FCI to R5C9A.F0 Memory_inst/SLICE_24
ROUTE 1 0.872 R5C9A.F0 to R5C10C.M0 Memory_inst/WriteCharNum_11
MTOOFX_DEL --- 0.345 R5C10C.M0 to R5C10C.OFX0 Memory_inst/SLICE_78
ROUTE 1 0.000 R5C10C.OFX0 to R5C10C.DI0 Memory_inst/WriteAddress_12_N_115_12 (to Clock_c)
--------
12.516 (30.1% logic, 69.9% route), 8 logic levels.
Clock Skew Details:
Source Clock Path Clock to Memory_inst/SLICE_51:
Name Fanout Delay (ns) Site Resource
ROUTE 121 2.001 20.PADDI to R8C8B.CLK Clock_c
--------
2.001 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path Clock to Memory_inst/SLICE_78:
Name Fanout Delay (ns) Site Resource
ROUTE 121 2.001 20.PADDI to R5C10C.CLK Clock_c
--------
2.001 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 27.428ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Memory_inst/CursorY_i1 (from Clock_c +)
Destination: FF Data in Memory_inst/WriteAddress_i11 (to Clock_c +)
Delay: 12.422ns (29.6% logic, 70.4% route), 7 logic levels.
Constraint Details:
12.422ns physical path delay Memory_inst/SLICE_51 to Memory_inst/SLICE_77 meets
40.000ns delay constraint less
0.000ns skew and
0.150ns DIN_SET requirement (totaling 39.850ns) by 27.428ns
Physical Path Details:
Data path Memory_inst/SLICE_51 to Memory_inst/SLICE_77:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R8C8B.CLK to R8C8B.Q1 Memory_inst/SLICE_51 (from Clock_c)
ROUTE 26 3.573 R8C8B.Q1 to R7C5D.D0 Memory_inst/CursorY_1
CTOF_DEL --- 0.452 R7C5D.D0 to R7C5D.F0 Memory_inst/SLICE_206
ROUTE 7 1.799 R7C5D.F0 to R4C5B.D0 Memory_inst/n5207
CTOOFX_DEL --- 0.661 R4C5B.D0 to R4C5B.OFX0 Memory_inst/i4422/SLICE_137
ROUTE 1 0.882 R4C5B.OFX0 to R4C6C.B0 Memory_inst/n4977
CTOF_DEL --- 0.452 R4C6C.B0 to R4C6C.F0 Memory_inst/SLICE_186
ROUTE 1 1.622 R4C6C.F0 to R5C8C.B1 Memory_inst/n4315
C1TOFCO_DE --- 0.786 R5C8C.B1 to R5C8C.FCO Memory_inst/SLICE_26
ROUTE 1 0.000 R5C8C.FCO to R5C8D.FCI Memory_inst/n3750
FCITOF1_DE --- 0.569 R5C8D.FCI to R5C8D.F1 Memory_inst/SLICE_21
ROUTE 1 0.872 R5C8D.F1 to R5C10B.M0 Memory_inst/WriteCharNum_10
MTOOFX_DEL --- 0.345 R5C10B.M0 to R5C10B.OFX0 Memory_inst/SLICE_77
ROUTE 1 0.000 R5C10B.OFX0 to R5C10B.DI0 Memory_inst/WriteAddress_12_N_115_11 (to Clock_c)
--------
12.422 (29.6% logic, 70.4% route), 7 logic levels.
Clock Skew Details:
Source Clock Path Clock to Memory_inst/SLICE_51:
Name Fanout Delay (ns) Site Resource
ROUTE 121 2.001 20.PADDI to R8C8B.CLK Clock_c
--------
2.001 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path Clock to Memory_inst/SLICE_77:
Name Fanout Delay (ns) Site Resource
ROUTE 121 2.001 20.PADDI to R5C10B.CLK Clock_c
--------
2.001 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 27.428ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Memory_inst/CursorY_i1 (from Clock_c +)
Destination: FF Data in Memory_inst/WriteAddress_i11 (to Clock_c +)
Delay: 12.422ns (29.6% logic, 70.4% route), 7 logic levels.
Constraint Details:
12.422ns physical path delay Memory_inst/SLICE_51 to Memory_inst/SLICE_77 meets
40.000ns delay constraint less
0.000ns skew and
0.150ns DIN_SET requirement (totaling 39.850ns) by 27.428ns
Physical Path Details:
Data path Memory_inst/SLICE_51 to Memory_inst/SLICE_77:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R8C8B.CLK to R8C8B.Q1 Memory_inst/SLICE_51 (from Clock_c)
ROUTE 26 3.573 R8C8B.Q1 to R7C5D.D0 Memory_inst/CursorY_1
CTOF_DEL --- 0.452 R7C5D.D0 to R7C5D.F0 Memory_inst/SLICE_206
ROUTE 7 1.799 R7C5D.F0 to R4C5B.D1 Memory_inst/n5207
CTOOFX_DEL --- 0.661 R4C5B.D1 to R4C5B.OFX0 Memory_inst/i4422/SLICE_137
ROUTE 1 0.882 R4C5B.OFX0 to R4C6C.B0 Memory_inst/n4977
CTOF_DEL --- 0.452 R4C6C.B0 to R4C6C.F0 Memory_inst/SLICE_186
ROUTE 1 1.622 R4C6C.F0 to R5C8C.B1 Memory_inst/n4315
C1TOFCO_DE --- 0.786 R5C8C.B1 to R5C8C.FCO Memory_inst/SLICE_26
ROUTE 1 0.000 R5C8C.FCO to R5C8D.FCI Memory_inst/n3750
FCITOF1_DE --- 0.569 R5C8D.FCI to R5C8D.F1 Memory_inst/SLICE_21
ROUTE 1 0.872 R5C8D.F1 to R5C10B.M0 Memory_inst/WriteCharNum_10
MTOOFX_DEL --- 0.345 R5C10B.M0 to R5C10B.OFX0 Memory_inst/SLICE_77
ROUTE 1 0.000 R5C10B.OFX0 to R5C10B.DI0 Memory_inst/WriteAddress_12_N_115_11 (to Clock_c)
--------
12.422 (29.6% logic, 70.4% route), 7 logic levels.
Clock Skew Details:
Source Clock Path Clock to Memory_inst/SLICE_51:
Name Fanout Delay (ns) Site Resource
ROUTE 121 2.001 20.PADDI to R8C8B.CLK Clock_c
--------
2.001 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path Clock to Memory_inst/SLICE_77:
Name Fanout Delay (ns) Site Resource
ROUTE 121 2.001 20.PADDI to R5C10B.CLK Clock_c
--------
2.001 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 27.830ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Memory_inst/CursorY_i1 (from Clock_c +)
Destination: FF Data in Memory_inst/WriteAddress_i10 (to Clock_c +)
Delay: 12.020ns (30.1% logic, 69.9% route), 7 logic levels.
Constraint Details:
12.020ns physical path delay Memory_inst/SLICE_51 to Memory_inst/SLICE_76 meets
40.000ns delay constraint less
0.000ns skew and
0.150ns DIN_SET requirement (totaling 39.850ns) by 27.830ns
Physical Path Details:
Data path Memory_inst/SLICE_51 to Memory_inst/SLICE_76:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R8C8B.CLK to R8C8B.Q1 Memory_inst/SLICE_51 (from Clock_c)
ROUTE 26 3.573 R8C8B.Q1 to R7C5D.D0 Memory_inst/CursorY_1
CTOF_DEL --- 0.452 R7C5D.D0 to R7C5D.F0 Memory_inst/SLICE_206
ROUTE 7 1.799 R7C5D.F0 to R4C5B.D0 Memory_inst/n5207
CTOOFX_DEL --- 0.661 R4C5B.D0 to R4C5B.OFX0 Memory_inst/i4422/SLICE_137
ROUTE 1 0.882 R4C5B.OFX0 to R4C6C.B0 Memory_inst/n4977
CTOF_DEL --- 0.452 R4C6C.B0 to R4C6C.F0 Memory_inst/SLICE_186
ROUTE 1 1.622 R4C6C.F0 to R5C8C.B1 Memory_inst/n4315
C1TOFCO_DE --- 0.786 R5C8C.B1 to R5C8C.FCO Memory_inst/SLICE_26
ROUTE 1 0.000 R5C8C.FCO to R5C8D.FCI Memory_inst/n3750
FCITOF0_DE --- 0.517 R5C8D.FCI to R5C8D.F0 Memory_inst/SLICE_21
ROUTE 1 0.522 R5C8D.F0 to R5C10D.M0 Memory_inst/WriteCharNum_9
MTOOFX_DEL --- 0.345 R5C10D.M0 to R5C10D.OFX0 Memory_inst/SLICE_76
ROUTE 1 0.000 R5C10D.OFX0 to R5C10D.DI0 Memory_inst/WriteAddress_12_N_115_10 (to Clock_c)
--------
12.020 (30.1% logic, 69.9% route), 7 logic levels.
Clock Skew Details:
Source Clock Path Clock to Memory_inst/SLICE_51:
Name Fanout Delay (ns) Site Resource
ROUTE 121 2.001 20.PADDI to R8C8B.CLK Clock_c
--------
2.001 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path Clock to Memory_inst/SLICE_76:
Name Fanout Delay (ns) Site Resource
ROUTE 121 2.001 20.PADDI to R5C10D.CLK Clock_c
--------
2.001 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 27.830ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Memory_inst/CursorY_i1 (from Clock_c +)
Destination: FF Data in Memory_inst/WriteAddress_i10 (to Clock_c +)
Delay: 12.020ns (30.1% logic, 69.9% route), 7 logic levels.
Constraint Details:
12.020ns physical path delay Memory_inst/SLICE_51 to Memory_inst/SLICE_76 meets
40.000ns delay constraint less
0.000ns skew and
0.150ns DIN_SET requirement (totaling 39.850ns) by 27.830ns
Physical Path Details:
Data path Memory_inst/SLICE_51 to Memory_inst/SLICE_76:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R8C8B.CLK to R8C8B.Q1 Memory_inst/SLICE_51 (from Clock_c)
ROUTE 26 3.573 R8C8B.Q1 to R7C5D.D0 Memory_inst/CursorY_1
CTOF_DEL --- 0.452 R7C5D.D0 to R7C5D.F0 Memory_inst/SLICE_206
ROUTE 7 1.799 R7C5D.F0 to R4C5B.D1 Memory_inst/n5207
CTOOFX_DEL --- 0.661 R4C5B.D1 to R4C5B.OFX0 Memory_inst/i4422/SLICE_137
ROUTE 1 0.882 R4C5B.OFX0 to R4C6C.B0 Memory_inst/n4977
CTOF_DEL --- 0.452 R4C6C.B0 to R4C6C.F0 Memory_inst/SLICE_186
ROUTE 1 1.622 R4C6C.F0 to R5C8C.B1 Memory_inst/n4315
C1TOFCO_DE --- 0.786 R5C8C.B1 to R5C8C.FCO Memory_inst/SLICE_26
ROUTE 1 0.000 R5C8C.FCO to R5C8D.FCI Memory_inst/n3750
FCITOF0_DE --- 0.517 R5C8D.FCI to R5C8D.F0 Memory_inst/SLICE_21
ROUTE 1 0.522 R5C8D.F0 to R5C10D.M0 Memory_inst/WriteCharNum_9
MTOOFX_DEL --- 0.345 R5C10D.M0 to R5C10D.OFX0 Memory_inst/SLICE_76
ROUTE 1 0.000 R5C10D.OFX0 to R5C10D.DI0 Memory_inst/WriteAddress_12_N_115_10 (to Clock_c)
--------
12.020 (30.1% logic, 69.9% route), 7 logic levels.
Clock Skew Details:
Source Clock Path Clock to Memory_inst/SLICE_51:
Name Fanout Delay (ns) Site Resource
ROUTE 121 2.001 20.PADDI to R8C8B.CLK Clock_c
--------
2.001 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path Clock to Memory_inst/SLICE_76:
Name Fanout Delay (ns) Site Resource
ROUTE 121 2.001 20.PADDI to R5C10D.CLK Clock_c
--------
2.001 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 27.912ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Memory_inst/CursorY_i1 (from Clock_c +)
Destination: FF Data in Memory_inst/WriteAddress_i12 (to Clock_c +)
Delay: 11.938ns (32.1% logic, 67.9% route), 7 logic levels.
Constraint Details:
11.938ns physical path delay Memory_inst/SLICE_51 to Memory_inst/SLICE_78 meets
40.000ns delay constraint less
0.000ns skew and
0.150ns DIN_SET requirement (totaling 39.850ns) by 27.912ns
Physical Path Details:
Data path Memory_inst/SLICE_51 to Memory_inst/SLICE_78:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R8C8B.CLK to R8C8B.Q1 Memory_inst/SLICE_51 (from Clock_c)
ROUTE 26 3.573 R8C8B.Q1 to R7C5D.D0 Memory_inst/CursorY_1
CTOF_DEL --- 0.452 R7C5D.D0 to R7C5D.F0 Memory_inst/SLICE_206
ROUTE 7 1.799 R7C5D.F0 to R4C7A.D0 Memory_inst/n5207
CTOOFX_DEL --- 0.661 R4C7A.D0 to R4C7A.OFX0 Memory_inst/i4414/SLICE_141
ROUTE 3 0.683 R4C7A.OFX0 to R4C7C.C1 Memory_inst/n4327
CTOOFX_DEL --- 0.661 R4C7C.C1 to R4C7C.OFX0 Memory_inst/i4550/SLICE_123
ROUTE 1 1.180 R4C7C.OFX0 to R5C8D.B1 Memory_inst/n5219
C1TOFCO_DE --- 0.786 R5C8D.B1 to R5C8D.FCO Memory_inst/SLICE_21
ROUTE 1 0.000 R5C8D.FCO to R5C9A.FCI Memory_inst/n3751
FCITOF0_DE --- 0.517 R5C9A.FCI to R5C9A.F0 Memory_inst/SLICE_24
ROUTE 1 0.872 R5C9A.F0 to R5C10C.M0 Memory_inst/WriteCharNum_11
MTOOFX_DEL --- 0.345 R5C10C.M0 to R5C10C.OFX0 Memory_inst/SLICE_78
ROUTE 1 0.000 R5C10C.OFX0 to R5C10C.DI0 Memory_inst/WriteAddress_12_N_115_12 (to Clock_c)
--------
11.938 (32.1% logic, 67.9% route), 7 logic levels.
Clock Skew Details:
Source Clock Path Clock to Memory_inst/SLICE_51:
Name Fanout Delay (ns) Site Resource
ROUTE 121 2.001 20.PADDI to R8C8B.CLK Clock_c
--------
2.001 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path Clock to Memory_inst/SLICE_78:
Name Fanout Delay (ns) Site Resource
ROUTE 121 2.001 20.PADDI to R5C10C.CLK Clock_c
--------
2.001 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 27.912ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Memory_inst/CursorY_i1 (from Clock_c +)
Destination: FF Data in Memory_inst/WriteAddress_i12 (to Clock_c +)
Delay: 11.938ns (32.1% logic, 67.9% route), 7 logic levels.
Constraint Details:
11.938ns physical path delay Memory_inst/SLICE_51 to Memory_inst/SLICE_78 meets
40.000ns delay constraint less
0.000ns skew and
0.150ns DIN_SET requirement (totaling 39.850ns) by 27.912ns
Physical Path Details:
Data path Memory_inst/SLICE_51 to Memory_inst/SLICE_78:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R8C8B.CLK to R8C8B.Q1 Memory_inst/SLICE_51 (from Clock_c)
ROUTE 26 3.573 R8C8B.Q1 to R7C5D.D0 Memory_inst/CursorY_1
CTOF_DEL --- 0.452 R7C5D.D0 to R7C5D.F0 Memory_inst/SLICE_206
ROUTE 7 1.799 R7C5D.F0 to R4C7A.D1 Memory_inst/n5207
CTOOFX_DEL --- 0.661 R4C7A.D1 to R4C7A.OFX0 Memory_inst/i4414/SLICE_141
ROUTE 3 0.683 R4C7A.OFX0 to R4C7C.C1 Memory_inst/n4327
CTOOFX_DEL --- 0.661 R4C7C.C1 to R4C7C.OFX0 Memory_inst/i4550/SLICE_123
ROUTE 1 1.180 R4C7C.OFX0 to R5C8D.B1 Memory_inst/n5219
C1TOFCO_DE --- 0.786 R5C8D.B1 to R5C8D.FCO Memory_inst/SLICE_21
ROUTE 1 0.000 R5C8D.FCO to R5C9A.FCI Memory_inst/n3751
FCITOF0_DE --- 0.517 R5C9A.FCI to R5C9A.F0 Memory_inst/SLICE_24
ROUTE 1 0.872 R5C9A.F0 to R5C10C.M0 Memory_inst/WriteCharNum_11
MTOOFX_DEL --- 0.345 R5C10C.M0 to R5C10C.OFX0 Memory_inst/SLICE_78
ROUTE 1 0.000 R5C10C.OFX0 to R5C10C.DI0 Memory_inst/WriteAddress_12_N_115_12 (to Clock_c)
--------
11.938 (32.1% logic, 67.9% route), 7 logic levels.
Clock Skew Details:
Source Clock Path Clock to Memory_inst/SLICE_51:
Name Fanout Delay (ns) Site Resource
ROUTE 121 2.001 20.PADDI to R8C8B.CLK Clock_c
--------
2.001 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path Clock to Memory_inst/SLICE_78:
Name Fanout Delay (ns) Site Resource
ROUTE 121 2.001 20.PADDI to R5C10C.CLK Clock_c
--------
2.001 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 27.991ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Memory_inst/CursorY_i1 (from Clock_c +)
Destination: FF Data in Memory_inst/WriteAddress_i9 (to Clock_c +)
Delay: 11.859ns (23.4% logic, 76.6% route), 6 logic levels.
Constraint Details:
11.859ns physical path delay Memory_inst/SLICE_51 to Memory_inst/SLICE_75 meets
40.000ns delay constraint less
0.000ns skew and
0.150ns DIN_SET requirement (totaling 39.850ns) by 27.991ns
Physical Path Details:
Data path Memory_inst/SLICE_51 to Memory_inst/SLICE_75:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R8C8B.CLK to R8C8B.Q1 Memory_inst/SLICE_51 (from Clock_c)
ROUTE 26 3.573 R8C8B.Q1 to R7C5D.D0 Memory_inst/CursorY_1
CTOF_DEL --- 0.452 R7C5D.D0 to R7C5D.F0 Memory_inst/SLICE_206
ROUTE 7 1.799 R7C5D.F0 to R4C5B.D0 Memory_inst/n5207
CTOOFX_DEL --- 0.661 R4C5B.D0 to R4C5B.OFX0 Memory_inst/i4422/SLICE_137
ROUTE 1 0.882 R4C5B.OFX0 to R4C6C.B0 Memory_inst/n4977
CTOF_DEL --- 0.452 R4C6C.B0 to R4C6C.F0 Memory_inst/SLICE_186
ROUTE 1 1.622 R4C6C.F0 to R5C8C.B1 Memory_inst/n4315
CTOF_DEL --- 0.452 R5C8C.B1 to R5C8C.F1 Memory_inst/SLICE_26
ROUTE 1 1.212 R5C8C.F1 to R7C9B.M0 Memory_inst/WriteCharNum_8
MTOOFX_DEL --- 0.345 R7C9B.M0 to R7C9B.OFX0 Memory_inst/SLICE_75
ROUTE 1 0.000 R7C9B.OFX0 to R7C9B.DI0 Memory_inst/WriteAddress_12_N_115_9 (to Clock_c)
--------
11.859 (23.4% logic, 76.6% route), 6 logic levels.
Clock Skew Details:
Source Clock Path Clock to Memory_inst/SLICE_51:
Name Fanout Delay (ns) Site Resource
ROUTE 121 2.001 20.PADDI to R8C8B.CLK Clock_c
--------
2.001 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path Clock to Memory_inst/SLICE_75:
Name Fanout Delay (ns) Site Resource
ROUTE 121 2.001 20.PADDI to R7C9B.CLK Clock_c
--------
2.001 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 27.991ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Memory_inst/CursorY_i1 (from Clock_c +)
Destination: FF Data in Memory_inst/WriteAddress_i9 (to Clock_c +)
Delay: 11.859ns (23.4% logic, 76.6% route), 6 logic levels.
Constraint Details:
11.859ns physical path delay Memory_inst/SLICE_51 to Memory_inst/SLICE_75 meets
40.000ns delay constraint less
0.000ns skew and
0.150ns DIN_SET requirement (totaling 39.850ns) by 27.991ns
Physical Path Details:
Data path Memory_inst/SLICE_51 to Memory_inst/SLICE_75:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R8C8B.CLK to R8C8B.Q1 Memory_inst/SLICE_51 (from Clock_c)
ROUTE 26 3.573 R8C8B.Q1 to R7C5D.D0 Memory_inst/CursorY_1
CTOF_DEL --- 0.452 R7C5D.D0 to R7C5D.F0 Memory_inst/SLICE_206
ROUTE 7 1.799 R7C5D.F0 to R4C5B.D1 Memory_inst/n5207
CTOOFX_DEL --- 0.661 R4C5B.D1 to R4C5B.OFX0 Memory_inst/i4422/SLICE_137
ROUTE 1 0.882 R4C5B.OFX0 to R4C6C.B0 Memory_inst/n4977
CTOF_DEL --- 0.452 R4C6C.B0 to R4C6C.F0 Memory_inst/SLICE_186
ROUTE 1 1.622 R4C6C.F0 to R5C8C.B1 Memory_inst/n4315
CTOF_DEL --- 0.452 R5C8C.B1 to R5C8C.F1 Memory_inst/SLICE_26
ROUTE 1 1.212 R5C8C.F1 to R7C9B.M0 Memory_inst/WriteCharNum_8
MTOOFX_DEL --- 0.345 R7C9B.M0 to R7C9B.OFX0 Memory_inst/SLICE_75
ROUTE 1 0.000 R7C9B.OFX0 to R7C9B.DI0 Memory_inst/WriteAddress_12_N_115_9 (to Clock_c)
--------
11.859 (23.4% logic, 76.6% route), 6 logic levels.
Clock Skew Details:
Source Clock Path Clock to Memory_inst/SLICE_51:
Name Fanout Delay (ns) Site Resource
ROUTE 121 2.001 20.PADDI to R8C8B.CLK Clock_c
--------
2.001 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path Clock to Memory_inst/SLICE_75:
Name Fanout Delay (ns) Site Resource
ROUTE 121 2.001 20.PADDI to R7C9B.CLK Clock_c
--------
2.001 (0.0% logic, 100.0% route), 0 logic levels.
Report: 78.952MHz is the maximum frequency for this preference.
Report Summary
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY PORT "Clock" 25.000000 MHz ; | 25.000 MHz| 78.952 MHz| 8
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 1 clocks:
Clock Domain: Clock_c Source: Clock.PAD Loads: 121
Covered under: FREQUENCY PORT "Clock" 25.000000 MHz ;
Timing summary (Setup):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 4806 paths, 1 nets, and 1765 connections (91.40% coverage)
--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.13.0.56.2
Thu Dec 19 19:34:40 2024
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2023 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 10 -gt -sethld -sp 5 -sphld m -o Kurs29_impl1.twr -gui -msgset C:/Lattice/Kurs29/promote.xml Kurs29_impl1.ncd Kurs29_impl1.prf
Design file: kurs29_impl1.ncd
Preference file: kurs29_impl1.prf
Device,speed: LCMXO2-1200HC,m
Report level: verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------
Preference Summary
FREQUENCY PORT "Clock" 25.000000 MHz (0 errors) 4096 items scored, 0 timing errors detected.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
BLOCK JTAG PATHS
--------------------------------------------------------------------------------
Derating parameters
-------------------
Voltage: 3.300 V
================================================================================
Preference: FREQUENCY PORT "Clock" 25.000000 MHz ;
4096 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.180ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Memory_inst/ReadAddress_i9 (from Clock_c +)
Destination: DP8KC Port Memory_inst/ImageRAM_3/Memory0(ASIC) (to Clock_c +)
Delay: 0.306ns (43.5% logic, 56.5% route), 1 logic levels.
Constraint Details:
0.306ns physical path delay Memory_inst/SLICE_28 to Memory_inst/ImageRAM_3/Memory0 meets
0.072ns ADDR_HLD and
0.000ns delay constraint less
-0.054ns skew requirement (totaling 0.126ns) by 0.180ns
Physical Path Details:
Data path Memory_inst/SLICE_28 to Memory_inst/ImageRAM_3/Memory0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R5C11C.CLK to R5C11C.Q0 Memory_inst/SLICE_28 (from Clock_c)
ROUTE 5 0.173 R5C11C.Q0 to *R_R6C10.ADB12 Memory_inst/ReadAddress_9 (to Clock_c)
--------
0.306 (43.5% logic, 56.5% route), 1 logic levels.
Clock Skew Details:
Source Clock Path Clock to Memory_inst/SLICE_28:
Name Fanout Delay (ns) Site Resource
ROUTE 121 0.773 20.PADDI to R5C11C.CLK Clock_c
--------
0.773 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path Clock to Memory_inst/ImageRAM_3/Memory0:
Name Fanout Delay (ns) Site Resource
ROUTE 121 0.827 20.PADDI to EBR_R6C10.CLKB Clock_c
--------
0.827 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.182ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Memory_inst/ReadAddress_i7 (from Clock_c +)
Destination: DP8KC Port Memory_inst/ImageRAM_3/Memory0(ASIC) (to Clock_c +)
Delay: 0.308ns (43.2% logic, 56.8% route), 1 logic levels.
Constraint Details:
0.308ns physical path delay Memory_inst/SLICE_22 to Memory_inst/ImageRAM_3/Memory0 meets
0.072ns ADDR_HLD and
0.000ns delay constraint less
-0.054ns skew requirement (totaling 0.126ns) by 0.182ns
Physical Path Details:
Data path Memory_inst/SLICE_22 to Memory_inst/ImageRAM_3/Memory0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R5C11B.CLK to R5C11B.Q0 Memory_inst/SLICE_22 (from Clock_c)
ROUTE 5 0.175 R5C11B.Q0 to *R_R6C10.ADB10 Memory_inst/ReadAddress_7 (to Clock_c)
--------
0.308 (43.2% logic, 56.8% route), 1 logic levels.
Clock Skew Details:
Source Clock Path Clock to Memory_inst/SLICE_22:
Name Fanout Delay (ns) Site Resource
ROUTE 121 0.773 20.PADDI to R5C11B.CLK Clock_c
--------
0.773 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path Clock to Memory_inst/ImageRAM_3/Memory0:
Name Fanout Delay (ns) Site Resource
ROUTE 121 0.827 20.PADDI to EBR_R6C10.CLKB Clock_c
--------
0.827 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.220ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Memory_inst/ReadAddress_i6 (from Clock_c +)
Destination: DP8KC Port Memory_inst/ImageRAM_3/Memory0(ASIC) (to Clock_c +)
Delay: 0.346ns (38.4% logic, 61.6% route), 1 logic levels.
Constraint Details:
0.346ns physical path delay Memory_inst/SLICE_23 to Memory_inst/ImageRAM_3/Memory0 meets
0.072ns ADDR_HLD and
0.000ns delay constraint less
-0.054ns skew requirement (totaling 0.126ns) by 0.220ns
Physical Path Details:
Data path Memory_inst/SLICE_23 to Memory_inst/ImageRAM_3/Memory0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R5C11A.CLK to R5C11A.Q1 Memory_inst/SLICE_23 (from Clock_c)
ROUTE 5 0.213 R5C11A.Q1 to EBR_R6C10.ADB9 Memory_inst/ReadAddress_6 (to Clock_c)
--------
0.346 (38.4% logic, 61.6% route), 1 logic levels.
Clock Skew Details:
Source Clock Path Clock to Memory_inst/SLICE_23:
Name Fanout Delay (ns) Site Resource
ROUTE 121 0.773 20.PADDI to R5C11A.CLK Clock_c
--------
0.773 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path Clock to Memory_inst/ImageRAM_3/Memory0:
Name Fanout Delay (ns) Site Resource
ROUTE 121 0.827 20.PADDI to EBR_R6C10.CLKB Clock_c
--------
0.827 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.301ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Memory_inst/ReadAddress_i4 (from Clock_c +)
Destination: DP8KC Port Memory_inst/ImageRAM_4/Memory0(ASIC) (to Clock_c +)
Delay: 0.427ns (31.1% logic, 68.9% route), 1 logic levels.
Constraint Details:
0.427ns physical path delay Memory_inst/SLICE_175 to Memory_inst/ImageRAM_4/Memory0 meets
0.072ns ADDR_HLD and
0.000ns delay constraint less
-0.054ns skew requirement (totaling 0.126ns) by 0.301ns
Physical Path Details:
Data path Memory_inst/SLICE_175 to Memory_inst/ImageRAM_4/Memory0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R4C8B.CLK to R4C8B.Q0 Memory_inst/SLICE_175 (from Clock_c)
ROUTE 5 0.294 R4C8B.Q0 to EBR_R6C7.ADB7 Memory_inst/ReadAddress_4 (to Clock_c)
--------
0.427 (31.1% logic, 68.9% route), 1 logic levels.
Clock Skew Details:
Source Clock Path Clock to Memory_inst/SLICE_175:
Name Fanout Delay (ns) Site Resource
ROUTE 121 0.773 20.PADDI to R4C8B.CLK Clock_c
--------
0.773 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path Clock to Memory_inst/ImageRAM_4/Memory0:
Name Fanout Delay (ns) Site Resource
ROUTE 121 0.827 20.PADDI to EBR_R6C7.CLKB Clock_c
--------
0.827 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.306ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Memory_inst/WriteAddress_i6 (from Clock_c +)
Destination: DP8KC Port Memory_inst/ImageRAM_4/Memory0(ASIC) (to Clock_c +)
Delay: 0.412ns (32.3% logic, 67.7% route), 1 logic levels.
Constraint Details:
0.412ns physical path delay Memory_inst/SLICE_72 to Memory_inst/ImageRAM_4/Memory0 meets
0.052ns ADDR_HLD and
0.000ns delay constraint less
-0.054ns skew requirement (totaling 0.106ns) by 0.306ns
Physical Path Details:
Data path Memory_inst/SLICE_72 to Memory_inst/ImageRAM_4/Memory0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R7C9D.CLK to R7C9D.Q0 Memory_inst/SLICE_72 (from Clock_c)
ROUTE 7 0.279 R7C9D.Q0 to EBR_R6C7.ADA9 Memory_inst/WriteAddress_6 (to Clock_c)
--------
0.412 (32.3% logic, 67.7% route), 1 logic levels.
Clock Skew Details:
Source Clock Path Clock to Memory_inst/SLICE_72:
Name Fanout Delay (ns) Site Resource
ROUTE 121 0.773 20.PADDI to R7C9D.CLK Clock_c
--------
0.773 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path Clock to Memory_inst/ImageRAM_4/Memory0:
Name Fanout Delay (ns) Site Resource
ROUTE 121 0.827 20.PADDI to EBR_R6C7.CLKA Clock_c
--------
0.827 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.306ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q UartRx_Inst/RxBuffer__i6 (from Clock_c +)
Destination: FF Data in UartRx_Inst/RxBuffer__i5 (to Clock_c +)
Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels.
Constraint Details:
0.287ns physical path delay SLICE_103 to SLICE_103 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.306ns
Physical Path Details:
Data path SLICE_103 to SLICE_103:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R8C12B.CLK to R8C12B.Q1 SLICE_103 (from Clock_c)
ROUTE 2 0.154 R8C12B.Q1 to R8C12B.M0 UartRx_Inst/RxBuffer_6 (to Clock_c)
--------
0.287 (46.3% logic, 53.7% route), 1 logic levels.
Clock Skew Details:
Source Clock Path Clock to SLICE_103:
Name Fanout Delay (ns) Site Resource
ROUTE 121 0.773 20.PADDI to R8C12B.CLK Clock_c
--------
0.773 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path Clock to SLICE_103:
Name Fanout Delay (ns) Site Resource
ROUTE 121 0.773 20.PADDI to R8C12B.CLK Clock_c
--------
0.773 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.306ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q UartRx_Inst/RxBuffer__i8 (from Clock_c +)
Destination: FF Data in UartRx_Inst/RxBuffer__i7 (to Clock_c +)
Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels.
Constraint Details:
0.287ns physical path delay SLICE_104 to SLICE_104 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.306ns
Physical Path Details:
Data path SLICE_104 to SLICE_104:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R7C12D.CLK to R7C12D.Q1 SLICE_104 (from Clock_c)
ROUTE 2 0.154 R7C12D.Q1 to R7C12D.M0 UartRx_Inst/RxBuffer_8 (to Clock_c)
--------
0.287 (46.3% logic, 53.7% route), 1 logic levels.
Clock Skew Details:
Source Clock Path Clock to SLICE_104:
Name Fanout Delay (ns) Site Resource
ROUTE 121 0.773 20.PADDI to R7C12D.CLK Clock_c
--------
0.773 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path Clock to SLICE_104:
Name Fanout Delay (ns) Site Resource
ROUTE 121 0.773 20.PADDI to R7C12D.CLK Clock_c
--------
0.773 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.306ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q UartRx_Inst/Synchronizer_Rx/R2_0__9 (from Clock_c +)
Destination: FF Data in UartRx_Inst/EdgeDetector_Rx/Previous_13 (to Clock_c +)
Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels.
Constraint Details:
0.287ns physical path delay SLICE_105 to SLICE_105 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.306ns
Physical Path Details:
Data path SLICE_105 to SLICE_105:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R7C8C.CLK to R7C8C.Q0 SLICE_105 (from Clock_c)
ROUTE 7 0.154 R7C8C.Q0 to R7C8C.M1 UartRx_Inst/RxSync (to Clock_c)
--------
0.287 (46.3% logic, 53.7% route), 1 logic levels.
Clock Skew Details:
Source Clock Path Clock to SLICE_105:
Name Fanout Delay (ns) Site Resource
ROUTE 121 0.773 20.PADDI to R7C8C.CLK Clock_c
--------
0.773 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path Clock to SLICE_105:
Name Fanout Delay (ns) Site Resource
ROUTE 121 0.773 20.PADDI to R7C8C.CLK Clock_c
--------
0.773 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.306ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q UartRx_Inst/RxBuffer__i4 (from Clock_c +)
Destination: FF Data in UartRx_Inst/RxBuffer__i3 (to Clock_c +)
Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels.
Constraint Details:
0.287ns physical path delay SLICE_166 to SLICE_166 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.306ns
Physical Path Details:
Data path SLICE_166 to SLICE_166:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R5C13C.CLK to R5C13C.Q1 SLICE_166 (from Clock_c)
ROUTE 2 0.154 R5C13C.Q1 to R5C13C.M0 UartRx_Inst/RxBuffer_4 (to Clock_c)
--------
0.287 (46.3% logic, 53.7% route), 1 logic levels.
Clock Skew Details:
Source Clock Path Clock to SLICE_166:
Name Fanout Delay (ns) Site Resource
ROUTE 121 0.773 20.PADDI to R5C13C.CLK Clock_c
--------
0.773 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path Clock to SLICE_166:
Name Fanout Delay (ns) Site Resource
ROUTE 121 0.773 20.PADDI to R5C13C.CLK Clock_c
--------
0.773 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.306ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q UartRx_Inst/RxBuffer__i2 (from Clock_c +)
Destination: FF Data in UartRx_Inst/RxBuffer__i1 (to Clock_c +)
Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels.
Constraint Details:
0.287ns physical path delay SLICE_171 to SLICE_171 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.306ns
Physical Path Details:
Data path SLICE_171 to SLICE_171:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R7C12C.CLK to R7C12C.Q1 SLICE_171 (from Clock_c)
ROUTE 2 0.154 R7C12C.Q1 to R7C12C.M0 UartRx_Inst/RxBuffer_2 (to Clock_c)
--------
0.287 (46.3% logic, 53.7% route), 1 logic levels.
Clock Skew Details:
Source Clock Path Clock to SLICE_171:
Name Fanout Delay (ns) Site Resource
ROUTE 121 0.773 20.PADDI to R7C12C.CLK Clock_c
--------
0.773 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path Clock to SLICE_171:
Name Fanout Delay (ns) Site Resource
ROUTE 121 0.773 20.PADDI to R7C12C.CLK Clock_c
--------
0.773 (0.0% logic, 100.0% route), 0 logic levels.
Report Summary
--------------
----------------------------------------------------------------------------
Preference(MIN Delays) | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY PORT "Clock" 25.000000 MHz ; | -| -| 1
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 1 clocks:
Clock Domain: Clock_c Source: Clock.PAD Loads: 121
Covered under: FREQUENCY PORT "Clock" 25.000000 MHz ;
Timing summary (Hold):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 4806 paths, 1 nets, and 1765 connections (91.40% coverage)
Timing summary (Setup and Hold):
---------------
Timing errors: 0 (setup), 0 (hold)
Score: 0 (setup), 0 (hold)
Cumulative negative slack: 0 (0+0)
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------