Lattice Mapping Report File for Design Module 'top'
Design Information
Command line: map -a MachXO2 -p LCMXO2-1200HC -t TQFP100 -s 5 -oc Commercial
Kurs29_impl1.ngd -o Kurs29_impl1_map.ncd -pr Kurs29_impl1.prf -mp
Kurs29_impl1.mrp -lpf C:/Lattice/Kurs29/impl1/Kurs29_impl1.lpf -lpf
C:/Lattice/Kurs29/Kurs29.lpf -c 0 -gui -msgset
C:/Lattice/Kurs29/promote.xml
Target Vendor: LATTICE
Target Device: LCMXO2-1200HCTQFP100
Target Performance: 5
Mapper: xo2c00, version: Diamond (64-bit) 3.13.0.56.2
Mapped on: 12/19/24 19:34:30
Design Summary
Number of registers: 168 out of 1520 (11%)
PFU registers: 168 out of 1280 (13%)
PIO registers: 0 out of 240 (0%)
Number of SLICEs: 206 out of 640 (32%)
SLICEs as Logic/ROM: 206 out of 640 (32%)
SLICEs as RAM: 0 out of 480 (0%)
SLICEs as Carry: 29 out of 640 (5%)
Number of LUT4s: 404 out of 1280 (32%)
Number used as logic LUTs: 346
Number used as distributed RAM: 0
Number used as ripple logic: 58
Number used as shift registers: 0
Number of PIO sites used: 24 + 4(JTAG) out of 80 (35%)
Number of block RAMs: 7 out of 7 (100%)
Number of GSRs: 1 out of 1 (100%)
EFB used : No
JTAG used : No
Readback used : No
Oscillator used : No
Startup used : No
POR : On
Bandgap : On
Number of Power Controller: 0 out of 1 (0%)
Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%)
Number of Dynamic Bank Controller (BCLVDSO): 0 out of 1 (0%)
Number of DCCA: 0 out of 8 (0%)
Number of DCMA: 0 out of 2 (0%)
Number of PLLs: 0 out of 1 (0%)
Number of DQSDLLs: 0 out of 2 (0%)
Number of CLKDIVC: 0 out of 4 (0%)
Number of ECLKSYNCA: 0 out of 4 (0%)
Number of ECLKBRIDGECS: 0 out of 2 (0%)
Notes:-
1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
distributed RAMs) + 2*(Number of ripple logic)
2. Number of logic LUT4s does not include count of distributed RAM and
ripple logic.
Number of clocks: 1
Net Clock_c: 121 loads, 121 rising, 0 falling (Driver: PIO Clock )
Number of Clock Enables: 25
Net DisplayMultiplex_inst/SwitchCathode_o: 2 loads, 2 LSLICEs
Net VGA_inst/Red_o_N_447: 1 loads, 1 LSLICEs
Net VGA_inst/Clock_c_enable_55: 6 loads, 6 LSLICEs
Net VGA_inst/Clock_c_enable_53: 1 loads, 1 LSLICEs
Net Memory_inst/WriteRequest_N_336: 17 loads, 17 LSLICEs
Net Memory_inst/Clock_c_enable_3: 1 loads, 1 LSLICEs
Net Memory_inst/Clock_c_enable_23: 7 loads, 7 LSLICEs
Net Memory_inst/Clock_c_enable_17: 3 loads, 3 LSLICEs
Net Memory_inst/Clock_c_enable_74: 7 loads, 7 LSLICEs
Net Memory_inst/Clock_c_enable_84: 6 loads, 6 LSLICEs
Net Memory_inst/Clock_c_enable_89: 8 loads, 8 LSLICEs
Net DataReceivedEvent: 4 loads, 4 LSLICEs
Net n5222: 1 loads, 1 LSLICEs
Net Memory_inst/Clock_c_enable_10: 1 loads, 1 LSLICEs
Net Memory_inst/DataFromImageRAM__4__7__N_211: 1 loads, 0 LSLICEs
Net Memory_inst/Clock_c_enable_56: 2 loads, 2 LSLICEs
Net Memory_inst/DataFromImageRAM__1__7__N_202: 1 loads, 0 LSLICEs
Net Memory_inst/DataFromImageRAM__3__7__N_208: 1 loads, 0 LSLICEs
Net Memory_inst/DataFromImageRAM__2__7__N_205: 1 loads, 0 LSLICEs
Net Memory_inst/DataFromImageRAM__0__7__N_199: 1 loads, 0 LSLICEs
Net UartRx_Inst/Clock_c_enable_62: 4 loads, 4 LSLICEs
Net UartRx_Inst/Clock_c_enable_30: 4 loads, 4 LSLICEs
Net UartRx_Inst/Clock_c_enable_54: 3 loads, 3 LSLICEs
Net UartRx_Inst/Busy_N_39: 2 loads, 2 LSLICEs
Net UartRx_Inst/Clock_c_enable_15: 1 loads, 1 LSLICEs
Number of LSRs: 12
Net DisplayMultiplex_inst/StrobeGenerator0/Strobe_o_N_524: 8 loads, 8
LSLICEs
Net Reset_c: 7 loads, 0 LSLICEs
Net VGA_inst/Red_o_N_447: 3 loads, 3 LSLICEs
Net VGA_inst/Clock_c_enable_55: 6 loads, 6 LSLICEs
Net VGA_inst/n2161: 6 loads, 6 LSLICEs
Net n2144: 2 loads, 2 LSLICEs
Net Memory_inst/Clock_c_enable_89: 2 loads, 2 LSLICEs
Net n5222: 1 loads, 1 LSLICEs
Net Memory_inst/n2152: 4 loads, 4 LSLICEs
Net UartRx_Inst/Busy: 2 loads, 2 LSLICEs
Net UartRx_Inst/n2170: 3 loads, 3 LSLICEs
Net UartRx_Inst/n273: 4 loads, 4 LSLICEs
Number of nets driven by tri-state buffers: 0
Top 10 highest fanout non-clock nets:
Net n5222: 51 loads
Net DataFromUART_7: 47 loads
Net Memory_inst/n2719: 42 loads
Net Memory_inst/CursorY_2: 39 loads
Net Memory_inst/CursorY_3: 39 loads
Net Memory_inst/CursorY_4: 39 loads
Net Memory_inst/CursorY_0: 26 loads
Net Memory_inst/CursorY_1: 26 loads
Net Memory_inst/ReadAddress_10: 19 loads
Net Memory_inst/WriteRequest_N_336: 18 loads
Number of warnings: 0
Number of errors: 0
Design Errors/Warnings
No errors or warnings present.
IO (PIO) Attributes
+---------------------+-----------+-----------+------------+
| IO Name | Direction | Levelmode | IO |
| | | IO_TYPE | Register |
+---------------------+-----------+-----------+------------+
| Cathodes_o[3] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Cathodes_o[4] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Cathodes_o[5] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Cathodes_o[6] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Cathodes_o[2] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Cathodes_o[7] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Cathodes_o[1] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Cathodes_o[0] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Segments_o[7] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Segments_o[6] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Segments_o[5] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Segments_o[4] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Segments_o[3] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Segments_o[2] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Segments_o[1] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Segments_o[0] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Red_o | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Green_o | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Blue_o | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| HSync_o | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| VSync_o | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Clock | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Reset | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| UartRx_i | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
Removed logic
Signal UartRx_Inst/n2146 was merged into signal UartRx_Inst/Busy
Signal Clock_c_enable_11 was merged into signal n5222
Signal Reset_N_405 was merged into signal Reset_c
Signal VCC_net undriven or does not drive anything - clipped.
Signal Memory_inst/mult_22_add_1_add_2_8/CO undriven or does not drive anything
- clipped.
Signal Memory_inst/add_166_9/S1 undriven or does not drive anything - clipped.
Signal Memory_inst/add_166_9/CO undriven or does not drive anything - clipped.
Signal Memory_inst/mult_22_add_1_add_2_2/S0 undriven or does not drive anything
- clipped.
Signal Memory_inst/mult_22_add_1_add_2_2/CI undriven or does not drive anything
- clipped.
Signal Memory_inst/add_166_1/S0 undriven or does not drive anything - clipped.
Signal Memory_inst/add_166_1/CI undriven or does not drive anything - clipped.
Signal VGA_inst/HCounter_382_add_4_11/S1 undriven or does not drive anything -
clipped.
Signal VGA_inst/HCounter_382_add_4_11/CO undriven or does not drive anything -
clipped.
Signal VGA_inst/VCounter_383_add_4_1/S0 undriven or does not drive anything -
clipped.
Signal VGA_inst/VCounter_383_add_4_1/CI undriven or does not drive anything -
clipped.
Signal VGA_inst/VCounter_383_add_4_11/S1 undriven or does not drive anything -
clipped.
Signal VGA_inst/VCounter_383_add_4_11/CO undriven or does not drive anything -
clipped.
Signal VGA_inst/HCounter_382_add_4_1/S0 undriven or does not drive anything -
clipped.
Signal VGA_inst/HCounter_382_add_4_1/CI undriven or does not drive anything -
clipped.
Signal DisplayMultiplex_inst/StrobeGenerator0/sub_6_add_2_1/S0 undriven or does
not drive anything - clipped.
Signal DisplayMultiplex_inst/StrobeGenerator0/sub_6_add_2_1/CI undriven or does
not drive anything - clipped.
Signal DisplayMultiplex_inst/StrobeGenerator0/sub_6_add_2_15/CO undriven or does
not drive anything - clipped.
Block UartRx_Inst/i1832_1_lut was optimized away.
Block UartRx_Inst/i386_1_lut was optimized away.
Block DisplayMultiplex_inst/StrobeGenerator0/Reset_I_0_1_lut was optimized away.
Block i5 was optimized away.
Memory Usage
/Memory_inst/FontROM:
EBRs: 2
RAM SLICEs: 0
Logic SLICEs: 1
PFU Registers: 1
-Contains EBR mux_31: TYPE= SP8KC, Width= 8, Depth= 1024, REGMODE=
NOREG, RESETMODE= ASYNC, ASYNC_RESET_RELEASE= SYNC, WRITEMODE=
NORMAL, GSR= DISABLED
-Contains EBR mux_30: TYPE= SP8KC, Width= 8, Depth= 1024, REGMODE=
NOREG, RESETMODE= ASYNC, ASYNC_RESET_RELEASE= SYNC, WRITEMODE=
NORMAL, GSR= DISABLED
/Memory_inst/ImageRAM_0:
EBRs: 1
RAM SLICEs: 0
Logic SLICEs: 0
PFU Registers: 0
-Contains EBR Memory0: TYPE= DP8KC, Width_B= 7, Depth_A= 1024, Depth_B=
1024, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
ASYNC_RESET_RELEASE= ASYNC, WRITEMODE_A= READBEFOREWRITE,
WRITEMODE_B= READBEFOREWRITE, GSR= DISABLED
/Memory_inst/ImageRAM_1:
EBRs: 1
RAM SLICEs: 0
Logic SLICEs: 0
PFU Registers: 0
-Contains EBR Memory0: TYPE= DP8KC, Width_B= 7, Depth_A= 1024, Depth_B=
1024, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
ASYNC_RESET_RELEASE= ASYNC, WRITEMODE_A= READBEFOREWRITE,
WRITEMODE_B= READBEFOREWRITE, GSR= DISABLED
/Memory_inst/ImageRAM_2:
EBRs: 1
RAM SLICEs: 0
Logic SLICEs: 0
PFU Registers: 0
-Contains EBR Memory0: TYPE= DP8KC, Width_B= 7, Depth_A= 1024, Depth_B=
1024, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
ASYNC_RESET_RELEASE= ASYNC, WRITEMODE_A= READBEFOREWRITE,
WRITEMODE_B= READBEFOREWRITE, GSR= DISABLED
/Memory_inst/ImageRAM_3:
EBRs: 1
RAM SLICEs: 0
Logic SLICEs: 0
PFU Registers: 0
-Contains EBR Memory0: TYPE= DP8KC, Width_B= 7, Depth_A= 1024, Depth_B=
1024, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
ASYNC_RESET_RELEASE= ASYNC, WRITEMODE_A= READBEFOREWRITE,
WRITEMODE_B= READBEFOREWRITE, GSR= DISABLED
/Memory_inst/ImageRAM_4:
EBRs: 1
RAM SLICEs: 0
Logic SLICEs: 0
PFU Registers: 0
-Contains EBR Memory0: TYPE= DP8KC, Width_B= 7, Depth_A= 1024, Depth_B=
1024, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC,
ASYNC_RESET_RELEASE= ASYNC, WRITEMODE_A= READBEFOREWRITE,
WRITEMODE_B= READBEFOREWRITE, GSR= DISABLED
ASIC Components
---------------
Instance Name: Memory_inst/ImageRAM_4/Memory0
Type: DP8KC
Instance Name: Memory_inst/ImageRAM_3/Memory0
Type: DP8KC
Instance Name: Memory_inst/ImageRAM_2/Memory0
Type: DP8KC
Instance Name: Memory_inst/ImageRAM_1/Memory0
Type: DP8KC
Instance Name: Memory_inst/ImageRAM_0/Memory0
Type: DP8KC
Instance Name: Memory_inst/FontROM/mux_31
Type: SP8KC
Instance Name: Memory_inst/FontROM/mux_30
Type: SP8KC
GSR Usage
---------
GSR Component:
The Global Set Reset (GSR) resource has been used to implement a global reset
of the design. The reset signal used for GSR control is 'Reset_c'.
GSR Property:
The design components with GSR property set to ENABLED will respond to global
set reset while the components with GSR property set to DISABLED will
not.
Components with disabled GSR Property
-------------------------------------
These components have the GSR property set to DISABLED. The components will
not respond to the reset signal 'Reset_c' via the GSR component.
Type and number of components of the type:
DP8KC = 5, SP8KC = 2
Type and instance name of component:
DP8KC : Memory_inst/ImageRAM_4/Memory0
DP8KC : Memory_inst/ImageRAM_3/Memory0
DP8KC : Memory_inst/ImageRAM_2/Memory0
DP8KC : Memory_inst/ImageRAM_1/Memory0
DP8KC : Memory_inst/ImageRAM_0/Memory0
SP8KC : Memory_inst/FontROM/mux_31
SP8KC : Memory_inst/FontROM/mux_30
Components with synchronous local reset also reset by asynchronous GSR
----------------------------------------------------------------------
These components have the GSR property set to ENABLED and the local reset
is synchronous. The components will respond to the synchronous local reset
and to the unrelated asynchronous reset signal 'Reset_c' via the GSR
component.
Type and number of components of the type:
Register = 67
Type and instance name of component:
Register : DisplayMultiplex_inst/StrobeGenerator0/Counter_i0
Register : DisplayMultiplex_inst/StrobeGenerator0/Counter_i1
Register : DisplayMultiplex_inst/StrobeGenerator0/Counter_i2
Register : DisplayMultiplex_inst/StrobeGenerator0/Counter_i3
Register : DisplayMultiplex_inst/StrobeGenerator0/Counter_i4
Register : DisplayMultiplex_inst/StrobeGenerator0/Counter_i5
Register : DisplayMultiplex_inst/StrobeGenerator0/Counter_i6
Register : DisplayMultiplex_inst/StrobeGenerator0/Counter_i7
Register : DisplayMultiplex_inst/StrobeGenerator0/Counter_i8
Register : DisplayMultiplex_inst/StrobeGenerator0/Counter_i9
Register : DisplayMultiplex_inst/StrobeGenerator0/Counter_i10
Register : DisplayMultiplex_inst/StrobeGenerator0/Counter_i11
Register : DisplayMultiplex_inst/StrobeGenerator0/Counter_i12
Register : DisplayMultiplex_inst/StrobeGenerator0/Counter_i13
Register : DisplayMultiplex_inst/StrobeGenerator0/Counter_i14
Register : VGA_inst/Red_o_65
Register : VGA_inst/HCounter_382__i0
Register : VGA_inst/Blue_o_63
Register : VGA_inst/Green_o_64
Register : VGA_inst/VCounter_383__i10
Register : VGA_inst/VCounter_383__i9
Register : VGA_inst/VCounter_383__i8
Register : VGA_inst/VCounter_383__i7
Register : VGA_inst/VCounter_383__i6
Register : VGA_inst/VCounter_383__i5
Register : VGA_inst/VCounter_383__i4
Register : VGA_inst/VCounter_383__i3
Register : VGA_inst/VCounter_383__i2
Register : VGA_inst/VCounter_383__i1
Register : VGA_inst/CharHCounter_i0
Register : VGA_inst/CharHCounter_i1
Register : VGA_inst/CharHCounter_i2
Register : VGA_inst/HCounter_382__i1
Register : VGA_inst/HCounter_382__i2
Register : VGA_inst/HCounter_382__i3
Register : VGA_inst/HCounter_382__i4
Register : VGA_inst/HCounter_382__i5
Register : VGA_inst/HCounter_382__i6
Register : VGA_inst/HCounter_382__i7
Register : VGA_inst/HCounter_382__i8
Register : VGA_inst/HCounter_382__i9
Register : Memory_inst/WriteStep1_124
Register : Memory_inst/ReadState_381__i2
Register : Memory_inst/ReadState_381__i1
Register : Memory_inst/Pixels_o_i7
Register : Memory_inst/Pixels_o_i6
Register : Memory_inst/Pixels_o_i5
Register : Memory_inst/Pixels_o_i4
Register : Memory_inst/Pixels_o_i3
Register : Memory_inst/Pixels_o_i2
Register : Memory_inst/Pixels_o_i1
Register : Memory_inst/ReadState_381__i0
Register : Memory_inst/Pixels_o_i0
Register : UartRx_Inst/Counter_380__i4
Register : UartRx_Inst/Counter_380__i3
Register : UartRx_Inst/Counter_380__i2
Register : UartRx_Inst/Counter_380__i1
Register : UartRx_Inst/Counter_380__i0
Register : UartRx_Inst/Done_o_33
Register : UartRx_Inst/Done_o_33_rep_110
Register : UartRx_Inst/StrobeGeneratorTicks_inst/Counter_i0
Register : UartRx_Inst/StrobeGeneratorTicks_inst/Counter_i1
Register : UartRx_Inst/StrobeGeneratorTicks_inst/Counter_i2
Register : UartRx_Inst/StrobeGeneratorTicks_inst/Counter_i3
Register : UartRx_Inst/StrobeGeneratorTicks_inst/Counter_i4
Register : UartRx_Inst/StrobeGeneratorTicks_inst/Counter_i5
Register : UartRx_Inst/StrobeGeneratorTicks_inst/Counter_i6
Run Time and Memory Usage
-------------------------
Total CPU Time: 0 secs
Total REAL Time: 0 secs
Peak Memory Usage: 43 MB
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Copyright (c) 2001 Agere Systems All rights reserved.
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