Lattice Synthesis Timing Report -------------------------------------------------------------------------------- Lattice Synthesis Timing Report, Version Mon Dec 26 10:58:12 2022 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Design: top Constraint file: Report level: verbose report, limited to 3 items per constraint -------------------------------------------------------------------------------- ================================================================================ Constraint: create_clock -period 5.000000 -name clk0 [get_nets Clock14MHz] 332 items scored, 152 timing errors detected. -------------------------------------------------------------------------------- Error: The following path violates requirements by 1.967ns Logical Details: Cell type Pin type Cell name (clock net +/-) Source: FD1S3IX CK \DebounceUp/Counter_50__i5 (from Clock14MHz +) Destination: FD1S3IX CD \DebounceUp/Counter_50__i5 (to Clock14MHz +) Delay: 6.807ns (28.3% logic, 71.7% route), 4 logic levels. Constraint Details: 6.807ns data_path \DebounceUp/Counter_50__i5 to \DebounceUp/Counter_50__i5 violates 5.000ns delay constraint less 0.160ns L_S requirement (totaling 4.840ns) by 1.967ns Path Details: \DebounceUp/Counter_50__i5 to \DebounceUp/Counter_50__i5 Name Fanout Delay (ns) Pins Resource(Cell.Net) L_CO --- 0.444 CK to Q \DebounceUp/Counter_50__i5 (from Clock14MHz) Route 2 e 1.198 \DebounceUp/Counter[5] LUT4 --- 0.493 A to Z \DebounceUp/i1_2_lut Route 1 e 0.941 \DebounceUp/n6 LUT4 --- 0.493 D to Z \DebounceUp/i4_4_lut Route 2 e 1.141 \DebounceUp/n464 LUT4 --- 0.493 D to Z \DebounceUp/i58_4_lut Route 10 e 1.604 \DebounceUp/n219 -------- 6.807 (28.3% logic, 71.7% route), 4 logic levels. Error: The following path violates requirements by 1.967ns Logical Details: Cell type Pin type Cell name (clock net +/-) Source: FD1S3IX CK \DebounceUp/Counter_50__i5 (from Clock14MHz +) Destination: FD1S3IX CD \DebounceUp/Counter_50__i4 (to Clock14MHz +) Delay: 6.807ns (28.3% logic, 71.7% route), 4 logic levels. Constraint Details: 6.807ns data_path \DebounceUp/Counter_50__i5 to \DebounceUp/Counter_50__i4 violates 5.000ns delay constraint less 0.160ns L_S requirement (totaling 4.840ns) by 1.967ns Path Details: \DebounceUp/Counter_50__i5 to \DebounceUp/Counter_50__i4 Name Fanout Delay (ns) Pins Resource(Cell.Net) L_CO --- 0.444 CK to Q \DebounceUp/Counter_50__i5 (from Clock14MHz) Route 2 e 1.198 \DebounceUp/Counter[5] LUT4 --- 0.493 A to Z \DebounceUp/i1_2_lut Route 1 e 0.941 \DebounceUp/n6 LUT4 --- 0.493 D to Z \DebounceUp/i4_4_lut Route 2 e 1.141 \DebounceUp/n464 LUT4 --- 0.493 D to Z \DebounceUp/i58_4_lut Route 10 e 1.604 \DebounceUp/n219 -------- 6.807 (28.3% logic, 71.7% route), 4 logic levels. Error: The following path violates requirements by 1.967ns Logical Details: Cell type Pin type Cell name (clock net +/-) Source: FD1S3IX CK \DebounceUp/Counter_50__i5 (from Clock14MHz +) Destination: FD1S3IX CD \DebounceUp/Counter_50__i0 (to Clock14MHz +) Delay: 6.807ns (28.3% logic, 71.7% route), 4 logic levels. Constraint Details: 6.807ns data_path \DebounceUp/Counter_50__i5 to \DebounceUp/Counter_50__i0 violates 5.000ns delay constraint less 0.160ns L_S requirement (totaling 4.840ns) by 1.967ns Path Details: \DebounceUp/Counter_50__i5 to \DebounceUp/Counter_50__i0 Name Fanout Delay (ns) Pins Resource(Cell.Net) L_CO --- 0.444 CK to Q \DebounceUp/Counter_50__i5 (from Clock14MHz) Route 2 e 1.198 \DebounceUp/Counter[5] LUT4 --- 0.493 A to Z \DebounceUp/i1_2_lut Route 1 e 0.941 \DebounceUp/n6 LUT4 --- 0.493 D to Z \DebounceUp/i4_4_lut Route 2 e 1.141 \DebounceUp/n464 LUT4 --- 0.493 D to Z \DebounceUp/i58_4_lut Route 10 e 1.604 \DebounceUp/n219 -------- 6.807 (28.3% logic, 71.7% route), 4 logic levels. Warning: 6.967 ns is the maximum delay for this constraint. Timing Report Summary -------------- -------------------------------------------------------------------------------- Constraint | Constraint| Actual|Levels -------------------------------------------------------------------------------- | | | create_clock -period 5.000000 -name | | | clk0 [get_nets Clock14MHz] | 5.000 ns| 6.967 ns| 4 * | | | -------------------------------------------------------------------------------- 1 constraints not met. -------------------------------------------------------------------------------- Critical Nets | Loads| Errors| % of total -------------------------------------------------------------------------------- \DebounceUp/n219 | 10| 70| 46.05% | | | \DebounceDown/n222 | 10| 60| 39.47% | | | \DebounceDown/n461 | 2| 52| 34.21% | | | \DebounceUp/n464 | 2| 52| 34.21% | | | \DebounceDown/n6 | 1| 22| 14.47% | | | \DebounceUp/n6 | 1| 22| 14.47% | | | \DebounceUp/n43 | 1| 20| 13.16% | | | -------------------------------------------------------------------------------- Timing summary: --------------- Timing errors: 152 Score: 144043 Constraints cover 332 paths, 80 nets, and 170 connections (79.1% coverage) Peak memory: 56225792 bytes, TRCE: 1765376 bytes, DLYMAN: 0 bytes CPU_TIME_REPORT: 0 secs