Lattice Synthesis Timing Report -------------------------------------------------------------------------------- Lattice Synthesis Timing Report, Version Sat Dec 31 10:22:26 2022 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Design: top Constraint file: Report level: verbose report, limited to 3 items per constraint -------------------------------------------------------------------------------- ================================================================================ Constraint: create_clock -period 5.000000 -name clk0 [get_nets Clock14MHz] 92 items scored, 43 timing errors detected. -------------------------------------------------------------------------------- Error: The following path violates requirements by 1.903ns Logical Details: Cell type Pin type Cell name (clock net +/-) Source: FD1P3AX CK \DebounceUp/FilteredSignal_17 (from Clock14MHz +) Destination: FD1S3AX D \Counter0/Value_i3 (to Clock14MHz +) Delay: 6.743ns (28.5% logic, 71.5% route), 4 logic levels. Constraint Details: 6.743ns data_path \DebounceUp/FilteredSignal_17 to \Counter0/Value_i3 violates 5.000ns delay constraint less 0.160ns L_S requirement (totaling 4.840ns) by 1.903ns Path Details: \DebounceUp/FilteredSignal_17 to \Counter0/Value_i3 Name Fanout Delay (ns) Pins Resource(Cell.Net) L_CO --- 0.444 CK to Q \DebounceUp/FilteredSignal_17 (from Clock14MHz) Route 4 e 1.398 ButtonUpFiltered LUT4 --- 0.493 B to Z \UpDetector/RisingEdge_I_0_2_lut_rep_14 Route 4 e 1.340 n402 LUT4 --- 0.493 B to Z \Counter0/i70_4_lut Route 2 e 1.141 n4 LUT4 --- 0.493 D to Z \Counter0/i2_4_lut Route 1 e 0.941 \Counter0/Value_3__N_23[3] -------- 6.743 (28.5% logic, 71.5% route), 4 logic levels. Error: The following path violates requirements by 1.903ns Logical Details: Cell type Pin type Cell name (clock net +/-) Source: FD1P3AX CK \DebounceUp/FilteredSignal_17 (from Clock14MHz +) Destination: FD1S3AX D \Counter0/Value_i2 (to Clock14MHz +) Delay: 6.743ns (28.5% logic, 71.5% route), 4 logic levels. Constraint Details: 6.743ns data_path \DebounceUp/FilteredSignal_17 to \Counter0/Value_i2 violates 5.000ns delay constraint less 0.160ns L_S requirement (totaling 4.840ns) by 1.903ns Path Details: \DebounceUp/FilteredSignal_17 to \Counter0/Value_i2 Name Fanout Delay (ns) Pins Resource(Cell.Net) L_CO --- 0.444 CK to Q \DebounceUp/FilteredSignal_17 (from Clock14MHz) Route 4 e 1.398 ButtonUpFiltered LUT4 --- 0.493 B to Z \UpDetector/RisingEdge_I_0_2_lut_rep_14 Route 4 e 1.340 n402 LUT4 --- 0.493 B to Z \Counter0/i70_4_lut Route 2 e 1.141 n4 LUT4 --- 0.493 D to Z \UpDetector/i2_3_lut_4_lut Route 1 e 0.941 Value_3__N_23[2] -------- 6.743 (28.5% logic, 71.5% route), 4 logic levels. Error: The following path violates requirements by 1.704ns Logical Details: Cell type Pin type Cell name (clock net +/-) Source: FD1P3AX CK \DebounceDown/FilteredSignal_17 (from Clock14MHz +) Destination: FD1S3AX D \Counter0/Value_i3 (to Clock14MHz +) Delay: 6.544ns (29.4% logic, 70.6% route), 4 logic levels. Constraint Details: 6.544ns data_path \DebounceDown/FilteredSignal_17 to \Counter0/Value_i3 violates 5.000ns delay constraint less 0.160ns L_S requirement (totaling 4.840ns) by 1.704ns Path Details: \DebounceDown/FilteredSignal_17 to \Counter0/Value_i3 Name Fanout Delay (ns) Pins Resource(Cell.Net) L_CO --- 0.444 CK to Q \DebounceDown/FilteredSignal_17 (from Clock14MHz) Route 4 e 1.398 ButtonDownFiltered LUT4 --- 0.493 B to Z \DownDetector/RisingEdge_I_0_2_lut_rep_13 Route 2 e 1.141 n401 LUT4 --- 0.493 C to Z \Counter0/i70_4_lut Route 2 e 1.141 n4 LUT4 --- 0.493 D to Z \Counter0/i2_4_lut Route 1 e 0.941 \Counter0/Value_3__N_23[3] -------- 6.544 (29.4% logic, 70.6% route), 4 logic levels. Warning: 6.903 ns is the maximum delay for this constraint. Timing Report Summary -------------- -------------------------------------------------------------------------------- Constraint | Constraint| Actual|Levels -------------------------------------------------------------------------------- | | | create_clock -period 5.000000 -name | | | clk0 [get_nets Clock14MHz] | 5.000 ns| 6.903 ns| 4 * | | | -------------------------------------------------------------------------------- 1 constraints not met. -------------------------------------------------------------------------------- Critical Nets | Loads| Errors| % of total -------------------------------------------------------------------------------- \DebounceDown/n189 | 4| 12| 27.91% | | | \DebounceDown/n400 | 1| 12| 27.91% | | | \DebounceUp/n187 | 4| 12| 27.91% | | | \DebounceUp/n403 | 1| 12| 27.91% | | | n4 | 2| 12| 27.91% | | | n402 | 4| 10| 23.26% | | | \Counter0/Value_3__N_23[3] | 1| 8| 18.60% | | | Value_3__N_23[2] | 1| 6| 13.95% | | | ButtonUpFiltered | 4| 5| 11.63% | | | \UpDetector/Previous | 2| 5| 11.63% | | | n401 | 2| 5| 11.63% | | | -------------------------------------------------------------------------------- Timing summary: --------------- Timing errors: 43 Score: 22292 Constraints cover 92 paths, 38 nets, and 102 connections (71.8% coverage) Peak memory: 54947840 bytes, TRCE: 1585152 bytes, DLYMAN: 0 bytes CPU_TIME_REPORT: 0 secs