Lattice Synthesis Timing Report
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Lattice Synthesis Timing Report, Version  
Sun Dec 25 21:22:03 2022

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Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
------------------
Design:     StrobeGenerator
Constraint file:  
Report level:    verbose report, limited to 3 items per constraint
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================================================================================
Constraint: create_clock -period 5.000000 -name clk0 [get_nets Clock_c]
            26 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed:  The following path meets requirements by 1.036ns

 Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)

   Source:         FD1S3IX    CK             Counter_17__i0  (from Clock_c +)
   Destination:    FD1S3IX    CD             Counter_17__i1  (to Clock_c +)

   Delay:                   3.804ns  (24.6% logic, 75.4% route), 2 logic levels.

 Constraint Details:

      3.804ns data_path Counter_17__i0 to Counter_17__i1 meets
      5.000ns delay constraint less
      0.160ns L_S requirement (totaling 4.840ns) by 1.036ns

 Path Details: Counter_17__i0 to Counter_17__i1

   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
L_CO        ---     0.444             CK to Q              Counter_17__i0 (from Clock_c)
Route         5   e 1.462                                  Counter[0]
LUT4        ---     0.493              A to Z              i76_4_lut
Route         5   e 1.405                                  Strobe_c
                  --------
                    3.804  (24.6% logic, 75.4% route), 2 logic levels.


Passed:  The following path meets requirements by 1.036ns

 Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)

   Source:         FD1S3IX    CK             Counter_17__i0  (from Clock_c +)
   Destination:    FD1S3IX    CD             Counter_17__i2  (to Clock_c +)

   Delay:                   3.804ns  (24.6% logic, 75.4% route), 2 logic levels.

 Constraint Details:

      3.804ns data_path Counter_17__i0 to Counter_17__i2 meets
      5.000ns delay constraint less
      0.160ns L_S requirement (totaling 4.840ns) by 1.036ns

 Path Details: Counter_17__i0 to Counter_17__i2

   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
L_CO        ---     0.444             CK to Q              Counter_17__i0 (from Clock_c)
Route         5   e 1.462                                  Counter[0]
LUT4        ---     0.493              A to Z              i76_4_lut
Route         5   e 1.405                                  Strobe_c
                  --------
                    3.804  (24.6% logic, 75.4% route), 2 logic levels.


Passed:  The following path meets requirements by 1.036ns

 Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)

   Source:         FD1S3IX    CK             Counter_17__i0  (from Clock_c +)
   Destination:    FD1S3IX    CD             Counter_17__i0  (to Clock_c +)

   Delay:                   3.804ns  (24.6% logic, 75.4% route), 2 logic levels.

 Constraint Details:

      3.804ns data_path Counter_17__i0 to Counter_17__i0 meets
      5.000ns delay constraint less
      0.160ns L_S requirement (totaling 4.840ns) by 1.036ns

 Path Details: Counter_17__i0 to Counter_17__i0

   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
L_CO        ---     0.444             CK to Q              Counter_17__i0 (from Clock_c)
Route         5   e 1.462                                  Counter[0]
LUT4        ---     0.493              A to Z              i76_4_lut
Route         5   e 1.405                                  Strobe_c
                  --------
                    3.804  (24.6% logic, 75.4% route), 2 logic levels.

Report: 3.964 ns is the maximum delay for this constraint.


Timing Report Summary
--------------
--------------------------------------------------------------------------------
Constraint                              |   Constraint|       Actual|Levels
--------------------------------------------------------------------------------
                                        |             |             |
create_clock -period 5.000000 -name     |             |             |
clk0 [get_nets Clock_c]                 |     5.000 ns|     3.964 ns|     2  
                                        |             |             |
--------------------------------------------------------------------------------


All constraints were met.



Timing summary:
---------------

Timing errors: 0  Score: 0

Constraints cover  26 paths, 10 nets, and 26 connections (92.9% coverage)


Peak memory: 53628928 bytes, TRCE: 1306624 bytes, DLYMAN: 0 bytes
CPU_TIME_REPORT: 0 secs