Lattice Mapping Report File for Design Module 'top'
Design Information
Command line: map -a MachXO2 -p LCMXO2-1200HC -t TQFP100 -s 5 -oc Commercial
Kurs26_impl1.ngd -o Kurs26_impl1_map.ncd -pr Kurs26_impl1.prf -mp
Kurs26_impl1.mrp -lpf C:/Lattice/Kurs26/impl1/Kurs26_impl1.lpf -lpf
C:/Lattice/Kurs26/Kurs26.lpf -c 0 -gui -msgset
C:/Lattice/Kurs26/promote.xml
Target Vendor: LATTICE
Target Device: LCMXO2-1200HCTQFP100
Target Performance: 5
Mapper: xo2c00, version: Diamond (64-bit) 3.13.0.56.2
Mapped on: 06/27/24 13:12:40
Design Summary
Number of registers: 79 out of 1520 (5%)
PFU registers: 79 out of 1280 (6%)
PIO registers: 0 out of 240 (0%)
Number of SLICEs: 51 out of 640 (8%)
SLICEs as Logic/ROM: 51 out of 640 (8%)
SLICEs as RAM: 0 out of 480 (0%)
SLICEs as Carry: 8 out of 640 (1%)
Number of LUT4s: 94 out of 1280 (7%)
Number used as logic LUTs: 78
Number used as distributed RAM: 0
Number used as ripple logic: 16
Number used as shift registers: 0
Number of PIO sites used: 22 + 4(JTAG) out of 80 (33%)
Number of block RAMs: 0 out of 7 (0%)
Number of GSRs: 1 out of 1 (100%)
EFB used : No
JTAG used : No
Readback used : No
Oscillator used : No
Startup used : No
POR : On
Bandgap : On
Number of Power Controller: 0 out of 1 (0%)
Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%)
Number of Dynamic Bank Controller (BCLVDSO): 0 out of 1 (0%)
Number of DCCA: 0 out of 8 (0%)
Number of DCMA: 0 out of 2 (0%)
Number of PLLs: 0 out of 1 (0%)
Number of DQSDLLs: 0 out of 2 (0%)
Number of CLKDIVC: 0 out of 4 (0%)
Number of ECLKSYNCA: 0 out of 4 (0%)
Number of ECLKBRIDGECS: 0 out of 2 (0%)
Notes:-
1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
distributed RAMs) + 2*(Number of ripple logic)
2. Number of logic LUT4s does not include count of distributed RAM and
ripple logic.
Number of clocks: 1
Net Clock_c: 42 loads, 42 rising, 0 falling (Driver: PIO Clock )
Number of Clock Enables: 5
Net ReceivedEvent: 16 loads, 16 LSLICEs
Net DisplayMultiplex_inst/SwitchCathode_o: 2 loads, 2 LSLICEs
Net SlaveSPI_inst/Clock_c_enable_16: 4 loads, 4 LSLICEs
Net SlaveSPI_inst/Clock_c_enable_13: 5 loads, 5 LSLICEs
Net SlaveSPI_inst/Clock_c_enable_18: 1 loads, 1 LSLICEs
Number of LSRs: 3
Net DisplayMultiplex_inst/StrobeGenerator0/Strobe_o_N_142: 8 loads, 8
LSLICEs
Net SlaveSPI_inst/n352: 1 loads, 1 LSLICEs
Net SlaveSPI_inst/n881: 2 loads, 2 LSLICEs
Number of nets driven by tri-state buffers: 0
Top 10 highest fanout non-clock nets:
Net DisplayMultiplex_inst/TempData_3_N_100_2: 30 loads
Net DisplayMultiplex_inst/TempData_3_N_100_3: 20 loads
Net DisplayMultiplex_inst/TempData_3_N_100_4: 20 loads
Net ReceivedEvent: 16 loads
Net DisplayMultiplex_inst/StrobeGenerator0/Strobe_o_N_142: 9 loads
Net DisplayMultiplex_inst/n703: 7 loads
Net DisplayMultiplex_inst/n759: 7 loads
Net DisplayMultiplex_inst/TempData_0: 7 loads
Net DisplayMultiplex_inst/TempData_2: 7 loads
Net DisplayMultiplex_inst/TempData_3: 7 loads
Number of warnings: 0
Number of errors: 0
Design Errors/Warnings
No errors or warnings present.
IO (PIO) Attributes
+---------------------+-----------+-----------+------------+
| IO Name | Direction | Levelmode | IO |
| | | IO_TYPE | Register |
+---------------------+-----------+-----------+------------+
| MISO | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| MOSI | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| SCK | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| CS | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Reset | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Clock | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Segments_o[0] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Segments_o[1] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Segments_o[2] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Segments_o[3] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Segments_o[4] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Segments_o[5] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Segments_o[6] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Segments_o[7] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Cathodes_o[0] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Cathodes_o[1] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Cathodes_o[2] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Cathodes_o[3] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Cathodes_o[4] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Cathodes_o[5] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Cathodes_o[6] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Cathodes_o[7] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
Removed logic
Block i705 undriven or does not drive anything - clipped.
Signal GND_net undriven or does not drive anything - clipped.
Signal VCC_net undriven or does not drive anything - clipped.
Signal DisplayMultiplex_inst/StrobeGenerator0/sub_6_add_2_1/S0 undriven or does
not drive anything - clipped.
Signal DisplayMultiplex_inst/StrobeGenerator0/sub_6_add_2_1/CI undriven or does
not drive anything - clipped.
Signal DisplayMultiplex_inst/StrobeGenerator0/sub_6_add_2_15/CO undriven or does
not drive anything - clipped.
Block i1 was optimized away.
GSR Usage
---------
GSR Component:
The Global Set Reset (GSR) resource has been used to implement a global reset
of the design. The reset signal used for GSR control is 'Reset_c'.
GSR Property:
The design components with GSR property set to ENABLED will respond to global
set reset while the components with GSR property set to DISABLED will
not.
Components with synchronous local reset also reset by asynchronous GSR
----------------------------------------------------------------------
These components have the GSR property set to ENABLED and the local reset
is synchronous. The components will respond to the synchronous local reset
and to the unrelated asynchronous reset signal 'Reset_c' via the GSR
component.
Type and number of components of the type:
Register = 19
Type and instance name of component:
Register : DisplayMultiplex_inst/StrobeGenerator0/Counter_i6
Register : DisplayMultiplex_inst/StrobeGenerator0/Counter_i5
Register : DisplayMultiplex_inst/StrobeGenerator0/Counter_i4
Register : DisplayMultiplex_inst/StrobeGenerator0/Counter_i3
Register : DisplayMultiplex_inst/StrobeGenerator0/Counter_i2
Register : DisplayMultiplex_inst/StrobeGenerator0/Counter_i1
Register : DisplayMultiplex_inst/StrobeGenerator0/Counter_i0
Register : DisplayMultiplex_inst/StrobeGenerator0/Counter_i14
Register : DisplayMultiplex_inst/StrobeGenerator0/Counter_i13
Register : DisplayMultiplex_inst/StrobeGenerator0/Counter_i12
Register : DisplayMultiplex_inst/StrobeGenerator0/Counter_i11
Register : DisplayMultiplex_inst/StrobeGenerator0/Counter_i10
Register : DisplayMultiplex_inst/StrobeGenerator0/Counter_i9
Register : DisplayMultiplex_inst/StrobeGenerator0/Counter_i8
Register : DisplayMultiplex_inst/StrobeGenerator0/Counter_i7
Register : SlaveSPI_inst/DataToSend_i0
Register : SlaveSPI_inst/BitCounter__i0
Register : SlaveSPI_inst/BitCounter__i2
Register : SlaveSPI_inst/BitCounter__i1
Run Time and Memory Usage
-------------------------
Total CPU Time: 0 secs
Total REAL Time: 0 secs
Peak Memory Usage: 40 MB
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