Setting log file to 'D:/Lattice/Kurs06/impl1/hdla_gen_hierarchy.html'. Starting: parse design source files (VERI-1482) Analyzing Verilog file 'D:/Lattice/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v' (VERI-1482) Analyzing Verilog file 'D:/Lattice/Kurs06/impl1/source/top.v' (VERI-1482) Analyzing Verilog file 'D:/Lattice/Kurs06/impl1/source/decoder7seg.v' (VERI-1482) Analyzing Verilog file 'D:/Lattice/Kurs06/impl1/source/edge_detector.v' (VERI-1482) Analyzing Verilog file 'D:/Lattice/Kurs06/impl1/source/counter.v' (VERI-1482) Analyzing Verilog file 'D:/Lattice/Kurs06/impl1/source/debouncer.v' INFO - D:/Lattice/Kurs06/impl1/source/top.v(1,8-1,11) (VERI-1018) compiling module 'top' INFO - D:/Lattice/Kurs06/impl1/source/top.v(1,1-82,10) (VERI-9000) elaborating module 'top' INFO - D:/Lattice/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1793,1-1798,10) (VERI-9000) elaborating module 'OSCH_uniq_1' INFO - D:/Lattice/Kurs06/impl1/source/debouncer.v(1,1-29,10) (VERI-9000) elaborating module 'Debouncer_uniq_1' INFO - D:/Lattice/Kurs06/impl1/source/debouncer.v(1,1-29,10) (VERI-9000) elaborating module 'Debouncer_uniq_2' INFO - D:/Lattice/Kurs06/impl1/source/edge_detector.v(1,1-20,10) (VERI-9000) elaborating module 'EdgeDetector_uniq_1' INFO - D:/Lattice/Kurs06/impl1/source/edge_detector.v(1,1-20,10) (VERI-9000) elaborating module 'EdgeDetector_uniq_2' INFO - D:/Lattice/Kurs06/impl1/source/counter.v(1,1-20,10) (VERI-9000) elaborating module 'Counter_uniq_1' INFO - D:/Lattice/Kurs06/impl1/source/decoder7seg.v(1,1-36,10) (VERI-9000) elaborating module 'Decoder7seg_uniq_1' Done: design load finished with (0) errors, and (0) warnings