Synthesis and Ngdbuild  Report
synthesis:  version Diamond (64-bit) 3.12.1.454

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
Sat Dec 31 10:22:25 2022


Command Line:  synthesis -f Kurs06_impl1_lattice.synproj -gui -msgset D:/Lattice/Kurs06/promote.xml 

Synthesis options:
The -a option is MachXO2.
The -s option is 4.
The -t option is TQFP100.
The -d option is LCMXO2-1200HC.
Using package TQFP100.
Using performance grade 4.
                                                          

##########################################################

### Lattice Family : MachXO2

### Device  : LCMXO2-1200HC

### Package : TQFP100

### Speed   : 4

##########################################################

                                                          

INFO - synthesis: User-Selected Strategy Settings
Optimization goal = Balanced
Top-level module name = top.
Target frequency = 200.000000 MHz.
Maximum fanout = 1000.
Timing path count = 3
BRAM utilization = 100.000000 %
DSP usage = true
DSP utilization = 100.000000 %
fsm_encoding_style = auto
resolve_mixed_drivers = 0
fix_gated_clocks = 1

Mux style = Auto
Use Carry Chain = true
carry_chain_length = 0
Loop Limit = 1950.
Use IO Insertion = TRUE
Use IO Reg = AUTO

Resource Sharing = TRUE
Propagate Constants = TRUE
Remove Duplicate Registers = TRUE
force_gsr = auto
ROM style = auto
RAM style = auto
The -comp option is FALSE.
The -syn option is FALSE.
-p D:/Lattice/Kurs06 (searchpath added)
-p D:/Lattice/diamond/3.12/ispfpga/xo2c00/data (searchpath added)
-p D:/Lattice/Kurs06/impl1 (searchpath added)
-p D:/Lattice/Kurs06 (searchpath added)
Verilog design file = D:/Lattice/Kurs06/impl1/source/top.v
Verilog design file = D:/Lattice/Kurs06/impl1/source/decoder7seg.v
Verilog design file = D:/Lattice/Kurs06/impl1/source/edge_detector.v
Verilog design file = D:/Lattice/Kurs06/impl1/source/counter.v
Verilog design file = D:/Lattice/Kurs06/impl1/source/debouncer.v
NGD file = Kurs06_impl1.ngd
-sdc option: SDC file input not used.
-lpf option: Output file option is ON.
Hardtimer checking is enabled (default). The -dt option is not used.
The -r option is OFF. [ Remove LOC Properties is OFF. ]
Technology check ok...

Analyzing Verilog file D:/Lattice/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
Compile design.
Compile Design Begin
Analyzing Verilog file d:/lattice/kurs06/impl1/source/top.v. VERI-1482
Analyzing Verilog file d:/lattice/kurs06/impl1/source/decoder7seg.v. VERI-1482
Analyzing Verilog file d:/lattice/kurs06/impl1/source/edge_detector.v. VERI-1482
Analyzing Verilog file d:/lattice/kurs06/impl1/source/counter.v. VERI-1482
Analyzing Verilog file d:/lattice/kurs06/impl1/source/debouncer.v. VERI-1482
Analyzing Verilog file D:/Lattice/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
Top module name (Verilog): top
INFO - synthesis: d:/lattice/kurs06/impl1/source/top.v(1): compiling module top. VERI-1018
INFO - synthesis: D:/Lattice/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1793): compiling module OSCH(NOM_FREQ="14.00"). VERI-1018
INFO - synthesis: d:/lattice/kurs06/impl1/source/debouncer.v(1): compiling module Debouncer(FREQUENCY_MHZ=14,PERIOD_US=1). VERI-1018
INFO - synthesis: d:/lattice/kurs06/impl1/source/edge_detector.v(1): compiling module EdgeDetector. VERI-1018
INFO - synthesis: d:/lattice/kurs06/impl1/source/counter.v(1): compiling module Counter. VERI-1018
INFO - synthesis: d:/lattice/kurs06/impl1/source/decoder7seg.v(1): compiling module Decoder7seg. VERI-1018
Loading NGL library 'D:/Lattice/diamond/3.12/ispfpga/xo2c00a/data/xo2alib.ngl'...
Loading NGL library 'D:/Lattice/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
Loading NGL library 'D:/Lattice/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
Loading NGL library 'D:/Lattice/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
Loading device for application map from file 'xo2c1200.nph' in environment: D:/Lattice/diamond/3.12/ispfpga.
Package Status:                     Final          Version 1.44.
Top-level module name = top.



GSR instance connected to net Reset_c.
Applying 200.000000 MHz constraint to all clocks

WARNING - synthesis: No user .sdc file.
Results of NGD DRC are available in top_drc.log.
Loading NGL library 'D:/Lattice/diamond/3.12/ispfpga/xo2c00a/data/xo2alib.ngl'...
Loading NGL library 'D:/Lattice/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
Loading NGL library 'D:/Lattice/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
Loading NGL library 'D:/Lattice/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
All blocks are expanded and NGD expansion is successful.
Writing NGD file Kurs06_impl1.ngd.

################### Begin Area Report (top)######################
Number of register bits => 16 of 1520 (1 % )
FD1P3AX => 2
FD1S3AX => 6
FD1S3IX => 8
GSR => 1
IB => 3
LUT4 => 28
OB => 7
OSCH => 1
################### End Area Report ##################

################### Begin BlackBox Report ######################
TSALL => 1
################### End BlackBox Report ##################

################### Begin Clock Report ######################
Clock Nets
Number of Clocks: 1
  Net : Clock14MHz, loads : 16
Clock Enable Nets
Number of Clock Enables: 2
Top 2 highest fanout Clock Enables:
  Net : DebounceDown/Clock14MHz_enable_1, loads : 1
  Net : DebounceUp/Clock14MHz_enable_2, loads : 1
Highest fanout non-clock nets
Top 10 highest fanout non-clock nets:
  Net : Counter0/CountValue_0, loads : 9
  Net : Counter0/CountValue_2, loads : 8
  Net : Counter0/CountValue_1, loads : 8
  Net : Counter0/CountValue_3, loads : 7
  Net : DebounceDown/Counter_1, loads : 5
  Net : DebounceDown/Counter_0, loads : 5
  Net : DebounceUp/Counter_1, loads : 5
  Net : DebounceUp/Counter_0, loads : 5
  Net : DebounceDown/Counter_2, loads : 4
  Net : DebounceDown/n189, loads : 4
################### End Clock Report ##################

Timing Report Summary
--------------
--------------------------------------------------------------------------------
Constraint                              |   Constraint|       Actual|Levels
--------------------------------------------------------------------------------
                                        |             |             |
create_clock -period 5.000000 -name     |             |             |
clk0 [get_nets Clock14MHz]              |  200.000 MHz|  144.865 MHz|     4 *
                                        |             |             |
--------------------------------------------------------------------------------


1 constraints not met.


Peak Memory Usage: 52.535  MB

--------------------------------------------------------------
Elapsed CPU time for LSE flow : 0.391  secs
--------------------------------------------------------------