-------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 Wed Jan 11 16:38:15 2023 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Design file: top Device,speed: LCMXO2-1200HC,M Report level: verbose report, limited to 10 items per preference -------------------------------------------------------------------------------- Derating parameters ------------------- Voltage: 3.300 V ================================================================================ Preference: FREQUENCY 10.000000 MHz ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY NET "Clock14MHz" 20.000000 MHz ; 10 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 0.309ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DebounceDown/FilteredSignal_17 (from Clock14MHz +) Destination: FF Data in DownDetector/Previous_13 (to Clock14MHz +) Delay: 0.290ns (45.9% logic, 54.1% route), 1 logic levels. Constraint Details: 0.290ns physical path delay SLICE_0 to SLICE_10 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.309ns Physical Path Details: Data path SLICE_0 to SLICE_10: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R5C3B.CLK to R5C3B.Q0 SLICE_0 (from Clock14MHz) ROUTE 5 0.157 R5C3B.Q0 to R4C3B.M0 ButtonDownFiltered (to Clock14MHz) -------- 0.290 (45.9% logic, 54.1% route), 1 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_0: Name Fanout Delay (ns) Site Resource ROUTE 10 1.216 OSC.OSC to R5C3B.CLK Clock14MHz -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_10: Name Fanout Delay (ns) Site Resource ROUTE 10 1.216 OSC.OSC to R4C3B.CLK Clock14MHz -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.315ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DebounceDown/Counter_52__i0 (from Clock14MHz +) Destination: FF Data in DebounceDown/FilteredSignal_17 (to Clock14MHz +) Delay: 0.291ns (45.7% logic, 54.3% route), 1 logic levels. Constraint Details: 0.291ns physical path delay DebounceDown/SLICE_4 to SLICE_0 meets -0.024ns CE_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.024ns) by 0.315ns Physical Path Details: Data path DebounceDown/SLICE_4 to SLICE_0: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R5C3A.CLK to R5C3A.Q0 DebounceDown/SLICE_4 (from Clock14MHz) ROUTE 5 0.158 R5C3A.Q0 to R5C3B.CE DebounceDown/Counter_0 (to Clock14MHz) -------- 0.291 (45.7% logic, 54.3% route), 1 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to DebounceDown/SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 10 1.216 OSC.OSC to R5C3A.CLK Clock14MHz -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_0: Name Fanout Delay (ns) Site Resource ROUTE 10 1.216 OSC.OSC to R5C3B.CLK Clock14MHz -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.315ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DebounceUp/Counter_50__i0 (from Clock14MHz +) Destination: FF Data in DebounceUp/FilteredSignal_17 (to Clock14MHz +) Delay: 0.291ns (45.7% logic, 54.3% route), 1 logic levels. Constraint Details: 0.291ns physical path delay DebounceUp/SLICE_6 to SLICE_1 meets -0.024ns CE_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.024ns) by 0.315ns Physical Path Details: Data path DebounceUp/SLICE_6 to SLICE_1: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R4C5A.CLK to R4C5A.Q0 DebounceUp/SLICE_6 (from Clock14MHz) ROUTE 5 0.158 R4C5A.Q0 to R4C5B.CE DebounceUp/Counter_0 (to Clock14MHz) -------- 0.291 (45.7% logic, 54.3% route), 1 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to DebounceUp/SLICE_6: Name Fanout Delay (ns) Site Resource ROUTE 10 1.216 OSC.OSC to R4C5A.CLK Clock14MHz -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 10 1.216 OSC.OSC to R4C5B.CLK Clock14MHz -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DebounceDown/Counter_52__i0 (from Clock14MHz +) Destination: FF Data in DebounceDown/Counter_52__i0 (to Clock14MHz +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay DebounceDown/SLICE_4 to DebounceDown/SLICE_4 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path DebounceDown/SLICE_4 to DebounceDown/SLICE_4: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R5C3A.CLK to R5C3A.Q0 DebounceDown/SLICE_4 (from Clock14MHz) ROUTE 5 0.132 R5C3A.Q0 to R5C3A.A0 DebounceDown/Counter_0 CTOF_DEL --- 0.101 R5C3A.A0 to R5C3A.F0 DebounceDown/SLICE_4 ROUTE 1 0.000 R5C3A.F0 to R5C3A.DI0 DebounceDown/Clock14MHz_enable_1 (to Clock14MHz) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to DebounceDown/SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 10 1.216 OSC.OSC to R5C3A.CLK Clock14MHz -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to DebounceDown/SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 10 1.216 OSC.OSC to R5C3A.CLK Clock14MHz -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DebounceDown/Counter_52__i2 (from Clock14MHz +) Destination: FF Data in DebounceDown/Counter_52__i2 (to Clock14MHz +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay DebounceDown/SLICE_5 to DebounceDown/SLICE_5 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path DebounceDown/SLICE_5 to DebounceDown/SLICE_5: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R5C3D.CLK to R5C3D.Q0 DebounceDown/SLICE_5 (from Clock14MHz) ROUTE 3 0.132 R5C3D.Q0 to R5C3D.A0 DebounceDown/Counter_2 CTOF_DEL --- 0.101 R5C3D.A0 to R5C3D.F0 DebounceDown/SLICE_5 ROUTE 1 0.000 R5C3D.F0 to R5C3D.DI0 DebounceDown/n23 (to Clock14MHz) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to DebounceDown/SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 10 1.216 OSC.OSC to R5C3D.CLK Clock14MHz -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to DebounceDown/SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 10 1.216 OSC.OSC to R5C3D.CLK Clock14MHz -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DebounceDown/Counter_52__i3 (from Clock14MHz +) Destination: FF Data in DebounceDown/Counter_52__i3 (to Clock14MHz +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay DebounceDown/SLICE_5 to DebounceDown/SLICE_5 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path DebounceDown/SLICE_5 to DebounceDown/SLICE_5: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R5C3D.CLK to R5C3D.Q1 DebounceDown/SLICE_5 (from Clock14MHz) ROUTE 2 0.132 R5C3D.Q1 to R5C3D.A1 DebounceDown/Counter_3 CTOF_DEL --- 0.101 R5C3D.A1 to R5C3D.F1 DebounceDown/SLICE_5 ROUTE 1 0.000 R5C3D.F1 to R5C3D.DI1 DebounceDown/n22 (to Clock14MHz) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to DebounceDown/SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 10 1.216 OSC.OSC to R5C3D.CLK Clock14MHz -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to DebounceDown/SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 10 1.216 OSC.OSC to R5C3D.CLK Clock14MHz -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DebounceUp/Counter_50__i0 (from Clock14MHz +) Destination: FF Data in DebounceUp/Counter_50__i0 (to Clock14MHz +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay DebounceUp/SLICE_6 to DebounceUp/SLICE_6 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path DebounceUp/SLICE_6 to DebounceUp/SLICE_6: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R4C5A.CLK to R4C5A.Q0 DebounceUp/SLICE_6 (from Clock14MHz) ROUTE 5 0.132 R4C5A.Q0 to R4C5A.A0 DebounceUp/Counter_0 CTOF_DEL --- 0.101 R4C5A.A0 to R4C5A.F0 DebounceUp/SLICE_6 ROUTE 1 0.000 R4C5A.F0 to R4C5A.DI0 DebounceUp/Clock14MHz_enable_2 (to Clock14MHz) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to DebounceUp/SLICE_6: Name Fanout Delay (ns) Site Resource ROUTE 10 1.216 OSC.OSC to R4C5A.CLK Clock14MHz -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to DebounceUp/SLICE_6: Name Fanout Delay (ns) Site Resource ROUTE 10 1.216 OSC.OSC to R4C5A.CLK Clock14MHz -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DebounceUp/Counter_50__i3 (from Clock14MHz +) Destination: FF Data in DebounceUp/Counter_50__i3 (to Clock14MHz +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay DebounceUp/SLICE_7 to DebounceUp/SLICE_7 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path DebounceUp/SLICE_7 to DebounceUp/SLICE_7: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R4C5C.CLK to R4C5C.Q1 DebounceUp/SLICE_7 (from Clock14MHz) ROUTE 2 0.132 R4C5C.Q1 to R4C5C.A1 DebounceUp/Counter_3 CTOF_DEL --- 0.101 R4C5C.A1 to R4C5C.F1 DebounceUp/SLICE_7 ROUTE 1 0.000 R4C5C.F1 to R4C5C.DI1 DebounceUp/n22 (to Clock14MHz) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to DebounceUp/SLICE_7: Name Fanout Delay (ns) Site Resource ROUTE 10 1.216 OSC.OSC to R4C5C.CLK Clock14MHz -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to DebounceUp/SLICE_7: Name Fanout Delay (ns) Site Resource ROUTE 10 1.216 OSC.OSC to R4C5C.CLK Clock14MHz -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DebounceUp/Counter_50__i2 (from Clock14MHz +) Destination: FF Data in DebounceUp/Counter_50__i2 (to Clock14MHz +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay DebounceUp/SLICE_7 to DebounceUp/SLICE_7 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path DebounceUp/SLICE_7 to DebounceUp/SLICE_7: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R4C5C.CLK to R4C5C.Q0 DebounceUp/SLICE_7 (from Clock14MHz) ROUTE 3 0.132 R4C5C.Q0 to R4C5C.A0 DebounceUp/Counter_2 CTOF_DEL --- 0.101 R4C5C.A0 to R4C5C.F0 DebounceUp/SLICE_7 ROUTE 1 0.000 R4C5C.F0 to R4C5C.DI0 DebounceUp/n23 (to Clock14MHz) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to DebounceUp/SLICE_7: Name Fanout Delay (ns) Site Resource ROUTE 10 1.216 OSC.OSC to R4C5C.CLK Clock14MHz -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to DebounceUp/SLICE_7: Name Fanout Delay (ns) Site Resource ROUTE 10 1.216 OSC.OSC to R4C5C.CLK Clock14MHz -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.380ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DebounceDown/FilteredSignal_17 (from Clock14MHz +) Destination: FF Data in DebounceDown/FilteredSignal_17 (to Clock14MHz +) Delay: 0.367ns (63.8% logic, 36.2% route), 2 logic levels. Constraint Details: 0.367ns physical path delay SLICE_0 to SLICE_0 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.380ns Physical Path Details: Data path SLICE_0 to SLICE_0: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R5C3B.CLK to R5C3B.Q0 SLICE_0 (from Clock14MHz) ROUTE 5 0.133 R5C3B.Q0 to R5C3B.A0 ButtonDownFiltered CTOF_DEL --- 0.101 R5C3B.A0 to R5C3B.F0 SLICE_0 ROUTE 1 0.000 R5C3B.F0 to R5C3B.DI0 n385 (to Clock14MHz) -------- 0.367 (63.8% logic, 36.2% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_0: Name Fanout Delay (ns) Site Resource ROUTE 10 1.216 OSC.OSC to R5C3B.CLK Clock14MHz -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_0: Name Fanout Delay (ns) Site Resource ROUTE 10 1.216 OSC.OSC to R5C3B.CLK Clock14MHz -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Report Summary -------------- ---------------------------------------------------------------------------- Preference(MIN Delays) | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY 10.000000 MHz ; | -| -| 0 | | | FREQUENCY NET "Clock14MHz" 20.000000 | | | MHz ; | 0.000 ns| 0.309 ns| 1 | | | ---------------------------------------------------------------------------- All preferences were met. Clock Domains Analysis ------------------------ Found 1 clocks: Clock Domain: Clock14MHz Source: OSCH_inst.OSC Loads: 10 Covered under: FREQUENCY NET "Clock14MHz" 20.000000 MHz ; Timing summary (Hold): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 78 paths, 1 nets, and 126 connections (96.92% coverage) Timing summary (Setup and Hold): --------------- Timing errors: 0 (setup), 0 (hold) Score: 0 (setup), 0 (hold) Cumulative negative slack: 0 (0+0)