Place & Route TRACE Report

Loading design for application trce from file kurs06_impl1.ncd.
Design name: top
NCD version: 3.3
Vendor:      LATTICE
Device:      LCMXO2-1200HC
Package:     TQFP100
Performance: 4
Loading device for application trce from file 'xo2c1200.nph' in environment: D:/Lattice/diamond/3.12/ispfpga.
Package Status:                     Final          Version 1.44.
Performance Hardware Data Status:   Final          Version 34.4.
Setup and Hold Report

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Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
Wed Jan 11 22:05:08 2023

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
------------------
Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o Kurs06_impl1.twr -gui -msgset D:/Lattice/Kurs06/promote.xml Kurs06_impl1.ncd Kurs06_impl1.prf 
Design file:     kurs06_impl1.ncd
Preference file: kurs06_impl1.prf
Device,speed:    LCMXO2-1200HC,4
Report level:    verbose report, limited to 10 items per preference
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Preference Summary

  • FREQUENCY NET "Clock14MHz" 14.000112 MHz (0 errors)
  • 78 items scored, 0 timing errors detected. Report: 216.357MHz is the maximum frequency for this preference. BLOCK ASYNCPATHS BLOCK RESETPATHS BLOCK JTAG PATHS -------------------------------------------------------------------------------- Derating parameters ------------------- Voltage: 3.300 V ================================================================================ Preference: FREQUENCY NET "Clock14MHz" 14.000112 MHz ; 78 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 66.806ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DebounceUp/FilteredSignal_17 (from Clock14MHz +) Destination: FF Data in Counter0/Value_i3 (to Clock14MHz +) Delay: 4.456ns (43.5% logic, 56.5% route), 4 logic levels. Constraint Details: 4.456ns physical path delay SLICE_1 to SLICE_3 meets 71.428ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 71.262ns) by 66.806ns Physical Path Details: Data path SLICE_1 to SLICE_3: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R4C5B.CLK to R4C5B.Q0 SLICE_1 (from Clock14MHz) ROUTE 5 1.032 R4C5B.Q0 to R4C5B.B1 ButtonUpFiltered CTOF_DEL --- 0.495 R4C5B.B1 to R4C5B.F1 SLICE_1 ROUTE 4 1.042 R4C5B.F1 to R4C3B.B1 n412 CTOF_DEL --- 0.495 R4C3B.B1 to R4C3B.F1 SLICE_10 ROUTE 2 0.445 R4C3B.F1 to R4C3D.C1 n4 CTOF_DEL --- 0.495 R4C3D.C1 to R4C3D.F1 SLICE_3 ROUTE 1 0.000 R4C3D.F1 to R4C3D.DI1 Counter0/Value_3_N_23_3 (to Clock14MHz) -------- 4.456 (43.5% logic, 56.5% route), 4 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 10 3.541 OSC.OSC to R4C5B.CLK Clock14MHz -------- 3.541 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 10 3.541 OSC.OSC to R4C3D.CLK Clock14MHz -------- 3.541 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 66.845ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q UpDetector/Previous_13 (from Clock14MHz +) Destination: FF Data in Counter0/Value_i3 (to Clock14MHz +) Delay: 4.417ns (43.9% logic, 56.1% route), 4 logic levels. Constraint Details: 4.417ns physical path delay SLICE_9 to SLICE_3 meets 71.428ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 71.262ns) by 66.845ns Physical Path Details: Data path SLICE_9 to SLICE_3: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R4C3C.CLK to R4C3C.Q0 SLICE_9 (from Clock14MHz) ROUTE 2 0.993 R4C3C.Q0 to R4C5B.A1 UpDetector/Previous CTOF_DEL --- 0.495 R4C5B.A1 to R4C5B.F1 SLICE_1 ROUTE 4 1.042 R4C5B.F1 to R4C3B.B1 n412 CTOF_DEL --- 0.495 R4C3B.B1 to R4C3B.F1 SLICE_10 ROUTE 2 0.445 R4C3B.F1 to R4C3D.C1 n4 CTOF_DEL --- 0.495 R4C3D.C1 to R4C3D.F1 SLICE_3 ROUTE 1 0.000 R4C3D.F1 to R4C3D.DI1 Counter0/Value_3_N_23_3 (to Clock14MHz) -------- 4.417 (43.9% logic, 56.1% route), 4 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_9: Name Fanout Delay (ns) Site Resource ROUTE 10 3.541 OSC.OSC to R4C3C.CLK Clock14MHz -------- 3.541 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 10 3.541 OSC.OSC to R4C3D.CLK Clock14MHz -------- 3.541 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 66.927ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DebounceUp/FilteredSignal_17 (from Clock14MHz +) Destination: FF Data in Counter0/Value_i2 (to Clock14MHz +) Delay: 4.335ns (44.7% logic, 55.3% route), 4 logic levels. Constraint Details: 4.335ns physical path delay SLICE_1 to SLICE_3 meets 71.428ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 71.262ns) by 66.927ns Physical Path Details: Data path SLICE_1 to SLICE_3: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R4C5B.CLK to R4C5B.Q0 SLICE_1 (from Clock14MHz) ROUTE 5 1.032 R4C5B.Q0 to R4C5B.B1 ButtonUpFiltered CTOF_DEL --- 0.495 R4C5B.B1 to R4C5B.F1 SLICE_1 ROUTE 4 1.042 R4C5B.F1 to R4C3B.B1 n412 CTOF_DEL --- 0.495 R4C3B.B1 to R4C3B.F1 SLICE_10 ROUTE 2 0.324 R4C3B.F1 to R4C3D.D0 n4 CTOF_DEL --- 0.495 R4C3D.D0 to R4C3D.F0 SLICE_3 ROUTE 1 0.000 R4C3D.F0 to R4C3D.DI0 Value_3_N_23_2 (to Clock14MHz) -------- 4.335 (44.7% logic, 55.3% route), 4 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 10 3.541 OSC.OSC to R4C5B.CLK Clock14MHz -------- 3.541 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 10 3.541 OSC.OSC to R4C3D.CLK Clock14MHz -------- 3.541 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 66.966ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q UpDetector/Previous_13 (from Clock14MHz +) Destination: FF Data in Counter0/Value_i2 (to Clock14MHz +) Delay: 4.296ns (45.1% logic, 54.9% route), 4 logic levels. Constraint Details: 4.296ns physical path delay SLICE_9 to SLICE_3 meets 71.428ns delay constraint less 0.000ns skew and 0.166ns DIN_SET requirement (totaling 71.262ns) by 66.966ns Physical Path Details: Data path SLICE_9 to SLICE_3: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R4C3C.CLK to R4C3C.Q0 SLICE_9 (from Clock14MHz) ROUTE 2 0.993 R4C3C.Q0 to R4C5B.A1 UpDetector/Previous CTOF_DEL --- 0.495 R4C5B.A1 to R4C5B.F1 SLICE_1 ROUTE 4 1.042 R4C5B.F1 to R4C3B.B1 n412 CTOF_DEL --- 0.495 R4C3B.B1 to R4C3B.F1 SLICE_10 ROUTE 2 0.324 R4C3B.F1 to R4C3D.D0 n4 CTOF_DEL --- 0.495 R4C3D.D0 to R4C3D.F0 SLICE_3 ROUTE 1 0.000 R4C3D.F0 to R4C3D.DI0 Value_3_N_23_2 (to Clock14MHz) -------- 4.296 (45.1% logic, 54.9% route), 4 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_9: Name Fanout Delay (ns) Site Resource ROUTE 10 3.541 OSC.OSC to R4C3C.CLK Clock14MHz -------- 3.541 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 10 3.541 OSC.OSC to R4C3D.CLK Clock14MHz -------- 3.541 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 67.022ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DebounceDown/Counter_52__i3 (from Clock14MHz +) Destination: FF Data in DebounceDown/Counter_52__i3 (to Clock14MHz +) FF DebounceDown/Counter_52__i2 Delay: 4.132ns (34.9% logic, 65.1% route), 3 logic levels. Constraint Details: 4.132ns physical path delay DebounceDown/SLICE_5 to DebounceDown/SLICE_5 meets 71.428ns delay constraint less 0.000ns skew and 0.274ns LSR_SET requirement (totaling 71.154ns) by 67.022ns Physical Path Details: Data path DebounceDown/SLICE_5 to DebounceDown/SLICE_5: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R5C3D.CLK to R5C3D.Q1 DebounceDown/SLICE_5 (from Clock14MHz) ROUTE 2 0.974 R5C3D.Q1 to R5C3B.A1 DebounceDown/Counter_3 CTOF_DEL --- 0.495 R5C3B.A1 to R5C3B.F1 SLICE_0 ROUTE 2 0.632 R5C3B.F1 to R4C3C.D1 n203 CTOF_DEL --- 0.495 R4C3C.D1 to R4C3C.F1 SLICE_9 ROUTE 2 1.084 R4C3C.F1 to R5C3D.LSR DebounceDown/n189 (to Clock14MHz) -------- 4.132 (34.9% logic, 65.1% route), 3 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to DebounceDown/SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 10 3.541 OSC.OSC to R5C3D.CLK Clock14MHz -------- 3.541 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to DebounceDown/SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 10 3.541 OSC.OSC to R5C3D.CLK Clock14MHz -------- 3.541 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 67.022ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DebounceDown/Counter_52__i3 (from Clock14MHz +) Destination: FF Data in DebounceDown/Counter_52__i1 (to Clock14MHz +) FF DebounceDown/Counter_52__i0 Delay: 4.132ns (34.9% logic, 65.1% route), 3 logic levels. Constraint Details: 4.132ns physical path delay DebounceDown/SLICE_5 to DebounceDown/SLICE_4 meets 71.428ns delay constraint less 0.000ns skew and 0.274ns LSR_SET requirement (totaling 71.154ns) by 67.022ns Physical Path Details: Data path DebounceDown/SLICE_5 to DebounceDown/SLICE_4: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R5C3D.CLK to R5C3D.Q1 DebounceDown/SLICE_5 (from Clock14MHz) ROUTE 2 0.974 R5C3D.Q1 to R5C3B.A1 DebounceDown/Counter_3 CTOF_DEL --- 0.495 R5C3B.A1 to R5C3B.F1 SLICE_0 ROUTE 2 0.632 R5C3B.F1 to R4C3C.D1 n203 CTOF_DEL --- 0.495 R4C3C.D1 to R4C3C.F1 SLICE_9 ROUTE 2 1.084 R4C3C.F1 to R5C3A.LSR DebounceDown/n189 (to Clock14MHz) -------- 4.132 (34.9% logic, 65.1% route), 3 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to DebounceDown/SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 10 3.541 OSC.OSC to R5C3D.CLK Clock14MHz -------- 3.541 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to DebounceDown/SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 10 3.541 OSC.OSC to R5C3A.CLK Clock14MHz -------- 3.541 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 67.230ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DebounceDown/Counter_52__i1 (from Clock14MHz +) Destination: FF Data in DebounceDown/Counter_52__i3 (to Clock14MHz +) FF DebounceDown/Counter_52__i2 Delay: 3.924ns (36.7% logic, 63.3% route), 3 logic levels. Constraint Details: 3.924ns physical path delay DebounceDown/SLICE_4 to DebounceDown/SLICE_5 meets 71.428ns delay constraint less 0.000ns skew and 0.274ns LSR_SET requirement (totaling 71.154ns) by 67.230ns Physical Path Details: Data path DebounceDown/SLICE_4 to DebounceDown/SLICE_5: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R5C3A.CLK to R5C3A.Q1 DebounceDown/SLICE_4 (from Clock14MHz) ROUTE 4 0.766 R5C3A.Q1 to R5C3B.C1 DebounceDown/Counter_1 CTOF_DEL --- 0.495 R5C3B.C1 to R5C3B.F1 SLICE_0 ROUTE 2 0.632 R5C3B.F1 to R4C3C.D1 n203 CTOF_DEL --- 0.495 R4C3C.D1 to R4C3C.F1 SLICE_9 ROUTE 2 1.084 R4C3C.F1 to R5C3D.LSR DebounceDown/n189 (to Clock14MHz) -------- 3.924 (36.7% logic, 63.3% route), 3 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to DebounceDown/SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 10 3.541 OSC.OSC to R5C3A.CLK Clock14MHz -------- 3.541 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to DebounceDown/SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 10 3.541 OSC.OSC to R5C3D.CLK Clock14MHz -------- 3.541 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 67.230ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DebounceDown/Counter_52__i1 (from Clock14MHz +) Destination: FF Data in DebounceDown/Counter_52__i1 (to Clock14MHz +) FF DebounceDown/Counter_52__i0 Delay: 3.924ns (36.7% logic, 63.3% route), 3 logic levels. Constraint Details: 3.924ns physical path delay DebounceDown/SLICE_4 to DebounceDown/SLICE_4 meets 71.428ns delay constraint less 0.000ns skew and 0.274ns LSR_SET requirement (totaling 71.154ns) by 67.230ns Physical Path Details: Data path DebounceDown/SLICE_4 to DebounceDown/SLICE_4: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R5C3A.CLK to R5C3A.Q1 DebounceDown/SLICE_4 (from Clock14MHz) ROUTE 4 0.766 R5C3A.Q1 to R5C3B.C1 DebounceDown/Counter_1 CTOF_DEL --- 0.495 R5C3B.C1 to R5C3B.F1 SLICE_0 ROUTE 2 0.632 R5C3B.F1 to R4C3C.D1 n203 CTOF_DEL --- 0.495 R4C3C.D1 to R4C3C.F1 SLICE_9 ROUTE 2 1.084 R4C3C.F1 to R5C3A.LSR DebounceDown/n189 (to Clock14MHz) -------- 3.924 (36.7% logic, 63.3% route), 3 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to DebounceDown/SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 10 3.541 OSC.OSC to R5C3A.CLK Clock14MHz -------- 3.541 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to DebounceDown/SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 10 3.541 OSC.OSC to R5C3A.CLK Clock14MHz -------- 3.541 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 67.348ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DebounceDown/Counter_52__i2 (from Clock14MHz +) Destination: FF Data in DebounceDown/Counter_52__i3 (to Clock14MHz +) FF DebounceDown/Counter_52__i2 Delay: 3.806ns (37.9% logic, 62.1% route), 3 logic levels. Constraint Details: 3.806ns physical path delay DebounceDown/SLICE_5 to DebounceDown/SLICE_5 meets 71.428ns delay constraint less 0.000ns skew and 0.274ns LSR_SET requirement (totaling 71.154ns) by 67.348ns Physical Path Details: Data path DebounceDown/SLICE_5 to DebounceDown/SLICE_5: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R5C3D.CLK to R5C3D.Q0 DebounceDown/SLICE_5 (from Clock14MHz) ROUTE 3 0.648 R5C3D.Q0 to R5C3B.D1 DebounceDown/Counter_2 CTOF_DEL --- 0.495 R5C3B.D1 to R5C3B.F1 SLICE_0 ROUTE 2 0.632 R5C3B.F1 to R4C3C.D1 n203 CTOF_DEL --- 0.495 R4C3C.D1 to R4C3C.F1 SLICE_9 ROUTE 2 1.084 R4C3C.F1 to R5C3D.LSR DebounceDown/n189 (to Clock14MHz) -------- 3.806 (37.9% logic, 62.1% route), 3 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to DebounceDown/SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 10 3.541 OSC.OSC to R5C3D.CLK Clock14MHz -------- 3.541 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to DebounceDown/SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 10 3.541 OSC.OSC to R5C3D.CLK Clock14MHz -------- 3.541 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 67.348ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DebounceDown/Counter_52__i2 (from Clock14MHz +) Destination: FF Data in DebounceDown/Counter_52__i1 (to Clock14MHz +) FF DebounceDown/Counter_52__i0 Delay: 3.806ns (37.9% logic, 62.1% route), 3 logic levels. Constraint Details: 3.806ns physical path delay DebounceDown/SLICE_5 to DebounceDown/SLICE_4 meets 71.428ns delay constraint less 0.000ns skew and 0.274ns LSR_SET requirement (totaling 71.154ns) by 67.348ns Physical Path Details: Data path DebounceDown/SLICE_5 to DebounceDown/SLICE_4: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.452 R5C3D.CLK to R5C3D.Q0 DebounceDown/SLICE_5 (from Clock14MHz) ROUTE 3 0.648 R5C3D.Q0 to R5C3B.D1 DebounceDown/Counter_2 CTOF_DEL --- 0.495 R5C3B.D1 to R5C3B.F1 SLICE_0 ROUTE 2 0.632 R5C3B.F1 to R4C3C.D1 n203 CTOF_DEL --- 0.495 R4C3C.D1 to R4C3C.F1 SLICE_9 ROUTE 2 1.084 R4C3C.F1 to R5C3A.LSR DebounceDown/n189 (to Clock14MHz) -------- 3.806 (37.9% logic, 62.1% route), 3 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to DebounceDown/SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 10 3.541 OSC.OSC to R5C3D.CLK Clock14MHz -------- 3.541 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to DebounceDown/SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 10 3.541 OSC.OSC to R5C3A.CLK Clock14MHz -------- 3.541 (0.0% logic, 100.0% route), 0 logic levels. Report: 216.357MHz is the maximum frequency for this preference. Report Summary -------------- ---------------------------------------------------------------------------- Preference | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY NET "Clock14MHz" 14.000112 | | | MHz ; | 14.000 MHz| 216.357 MHz| 4 | | | ---------------------------------------------------------------------------- All preferences were met. Clock Domains Analysis ------------------------ Found 1 clocks: Clock Domain: Clock14MHz Source: OSCH_inst.OSC Loads: 10 Covered under: FREQUENCY NET "Clock14MHz" 14.000112 MHz ; Timing summary (Setup): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 78 paths, 1 nets, and 126 connections (96.92% coverage) -------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 Wed Jan 11 22:05:08 2023 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o Kurs06_impl1.twr -gui -msgset D:/Lattice/Kurs06/promote.xml Kurs06_impl1.ncd Kurs06_impl1.prf Design file: kurs06_impl1.ncd Preference file: kurs06_impl1.prf Device,speed: LCMXO2-1200HC,m Report level: verbose report, limited to 10 items per preference -------------------------------------------------------------------------------- Preference Summary
  • FREQUENCY NET "Clock14MHz" 14.000112 MHz (0 errors)
  • 78 items scored, 0 timing errors detected. BLOCK ASYNCPATHS BLOCK RESETPATHS BLOCK JTAG PATHS -------------------------------------------------------------------------------- Derating parameters ------------------- Voltage: 3.300 V ================================================================================ Preference: FREQUENCY NET "Clock14MHz" 14.000112 MHz ; 78 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 0.309ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DebounceDown/FilteredSignal_17 (from Clock14MHz +) Destination: FF Data in DownDetector/Previous_13 (to Clock14MHz +) Delay: 0.290ns (45.9% logic, 54.1% route), 1 logic levels. Constraint Details: 0.290ns physical path delay SLICE_0 to SLICE_10 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.309ns Physical Path Details: Data path SLICE_0 to SLICE_10: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R5C3B.CLK to R5C3B.Q0 SLICE_0 (from Clock14MHz) ROUTE 5 0.157 R5C3B.Q0 to R4C3B.M0 ButtonDownFiltered (to Clock14MHz) -------- 0.290 (45.9% logic, 54.1% route), 1 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to SLICE_0: Name Fanout Delay (ns) Site Resource ROUTE 10 1.216 OSC.OSC to R5C3B.CLK Clock14MHz -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_10: Name Fanout Delay (ns) Site Resource ROUTE 10 1.216 OSC.OSC to R4C3B.CLK Clock14MHz -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.315ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DebounceDown/Counter_52__i0 (from Clock14MHz +) Destination: FF Data in DebounceDown/FilteredSignal_17 (to Clock14MHz +) Delay: 0.291ns (45.7% logic, 54.3% route), 1 logic levels. Constraint Details: 0.291ns physical path delay DebounceDown/SLICE_4 to SLICE_0 meets -0.024ns CE_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.024ns) by 0.315ns Physical Path Details: Data path DebounceDown/SLICE_4 to SLICE_0: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R5C3A.CLK to R5C3A.Q0 DebounceDown/SLICE_4 (from Clock14MHz) ROUTE 5 0.158 R5C3A.Q0 to R5C3B.CE DebounceDown/Counter_0 (to Clock14MHz) -------- 0.291 (45.7% logic, 54.3% route), 1 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to DebounceDown/SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 10 1.216 OSC.OSC to R5C3A.CLK Clock14MHz -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_0: Name Fanout Delay (ns) Site Resource ROUTE 10 1.216 OSC.OSC to R5C3B.CLK Clock14MHz -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.315ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DebounceUp/Counter_50__i0 (from Clock14MHz +) Destination: FF Data in DebounceUp/FilteredSignal_17 (to Clock14MHz +) Delay: 0.291ns (45.7% logic, 54.3% route), 1 logic levels. Constraint Details: 0.291ns physical path delay DebounceUp/SLICE_6 to SLICE_1 meets -0.024ns CE_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.024ns) by 0.315ns Physical Path Details: Data path DebounceUp/SLICE_6 to SLICE_1: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R4C5A.CLK to R4C5A.Q0 DebounceUp/SLICE_6 (from Clock14MHz) ROUTE 5 0.158 R4C5A.Q0 to R4C5B.CE DebounceUp/Counter_0 (to Clock14MHz) -------- 0.291 (45.7% logic, 54.3% route), 1 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to DebounceUp/SLICE_6: Name Fanout Delay (ns) Site Resource ROUTE 10 1.216 OSC.OSC to R4C5A.CLK Clock14MHz -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 10 1.216 OSC.OSC to R4C5B.CLK Clock14MHz -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DebounceUp/Counter_50__i3 (from Clock14MHz +) Destination: FF Data in DebounceUp/Counter_50__i3 (to Clock14MHz +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay DebounceUp/SLICE_7 to DebounceUp/SLICE_7 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path DebounceUp/SLICE_7 to DebounceUp/SLICE_7: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R4C5C.CLK to R4C5C.Q1 DebounceUp/SLICE_7 (from Clock14MHz) ROUTE 2 0.132 R4C5C.Q1 to R4C5C.A1 DebounceUp/Counter_3 CTOF_DEL --- 0.101 R4C5C.A1 to R4C5C.F1 DebounceUp/SLICE_7 ROUTE 1 0.000 R4C5C.F1 to R4C5C.DI1 DebounceUp/n22 (to Clock14MHz) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to DebounceUp/SLICE_7: Name Fanout Delay (ns) Site Resource ROUTE 10 1.216 OSC.OSC to R4C5C.CLK Clock14MHz -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to DebounceUp/SLICE_7: Name Fanout Delay (ns) Site Resource ROUTE 10 1.216 OSC.OSC to R4C5C.CLK Clock14MHz -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DebounceUp/Counter_50__i2 (from Clock14MHz +) Destination: FF Data in DebounceUp/Counter_50__i2 (to Clock14MHz +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay DebounceUp/SLICE_7 to DebounceUp/SLICE_7 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path DebounceUp/SLICE_7 to DebounceUp/SLICE_7: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R4C5C.CLK to R4C5C.Q0 DebounceUp/SLICE_7 (from Clock14MHz) ROUTE 3 0.132 R4C5C.Q0 to R4C5C.A0 DebounceUp/Counter_2 CTOF_DEL --- 0.101 R4C5C.A0 to R4C5C.F0 DebounceUp/SLICE_7 ROUTE 1 0.000 R4C5C.F0 to R4C5C.DI0 DebounceUp/n23 (to Clock14MHz) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to DebounceUp/SLICE_7: Name Fanout Delay (ns) Site Resource ROUTE 10 1.216 OSC.OSC to R4C5C.CLK Clock14MHz -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to DebounceUp/SLICE_7: Name Fanout Delay (ns) Site Resource ROUTE 10 1.216 OSC.OSC to R4C5C.CLK Clock14MHz -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DebounceUp/Counter_50__i0 (from Clock14MHz +) Destination: FF Data in DebounceUp/Counter_50__i0 (to Clock14MHz +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay DebounceUp/SLICE_6 to DebounceUp/SLICE_6 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path DebounceUp/SLICE_6 to DebounceUp/SLICE_6: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R4C5A.CLK to R4C5A.Q0 DebounceUp/SLICE_6 (from Clock14MHz) ROUTE 5 0.132 R4C5A.Q0 to R4C5A.A0 DebounceUp/Counter_0 CTOF_DEL --- 0.101 R4C5A.A0 to R4C5A.F0 DebounceUp/SLICE_6 ROUTE 1 0.000 R4C5A.F0 to R4C5A.DI0 DebounceUp/Clock14MHz_enable_2 (to Clock14MHz) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to DebounceUp/SLICE_6: Name Fanout Delay (ns) Site Resource ROUTE 10 1.216 OSC.OSC to R4C5A.CLK Clock14MHz -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to DebounceUp/SLICE_6: Name Fanout Delay (ns) Site Resource ROUTE 10 1.216 OSC.OSC to R4C5A.CLK Clock14MHz -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DebounceDown/Counter_52__i0 (from Clock14MHz +) Destination: FF Data in DebounceDown/Counter_52__i0 (to Clock14MHz +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay DebounceDown/SLICE_4 to DebounceDown/SLICE_4 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path DebounceDown/SLICE_4 to DebounceDown/SLICE_4: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R5C3A.CLK to R5C3A.Q0 DebounceDown/SLICE_4 (from Clock14MHz) ROUTE 5 0.132 R5C3A.Q0 to R5C3A.A0 DebounceDown/Counter_0 CTOF_DEL --- 0.101 R5C3A.A0 to R5C3A.F0 DebounceDown/SLICE_4 ROUTE 1 0.000 R5C3A.F0 to R5C3A.DI0 DebounceDown/Clock14MHz_enable_1 (to Clock14MHz) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to DebounceDown/SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 10 1.216 OSC.OSC to R5C3A.CLK Clock14MHz -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to DebounceDown/SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 10 1.216 OSC.OSC to R5C3A.CLK Clock14MHz -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DebounceDown/Counter_52__i2 (from Clock14MHz +) Destination: FF Data in DebounceDown/Counter_52__i2 (to Clock14MHz +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay DebounceDown/SLICE_5 to DebounceDown/SLICE_5 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path DebounceDown/SLICE_5 to DebounceDown/SLICE_5: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R5C3D.CLK to R5C3D.Q0 DebounceDown/SLICE_5 (from Clock14MHz) ROUTE 3 0.132 R5C3D.Q0 to R5C3D.A0 DebounceDown/Counter_2 CTOF_DEL --- 0.101 R5C3D.A0 to R5C3D.F0 DebounceDown/SLICE_5 ROUTE 1 0.000 R5C3D.F0 to R5C3D.DI0 DebounceDown/n23 (to Clock14MHz) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to DebounceDown/SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 10 1.216 OSC.OSC to R5C3D.CLK Clock14MHz -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to DebounceDown/SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 10 1.216 OSC.OSC to R5C3D.CLK Clock14MHz -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.379ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DebounceDown/Counter_52__i3 (from Clock14MHz +) Destination: FF Data in DebounceDown/Counter_52__i3 (to Clock14MHz +) Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.366ns physical path delay DebounceDown/SLICE_5 to DebounceDown/SLICE_5 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.379ns Physical Path Details: Data path DebounceDown/SLICE_5 to DebounceDown/SLICE_5: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R5C3D.CLK to R5C3D.Q1 DebounceDown/SLICE_5 (from Clock14MHz) ROUTE 2 0.132 R5C3D.Q1 to R5C3D.A1 DebounceDown/Counter_3 CTOF_DEL --- 0.101 R5C3D.A1 to R5C3D.F1 DebounceDown/SLICE_5 ROUTE 1 0.000 R5C3D.F1 to R5C3D.DI1 DebounceDown/n22 (to Clock14MHz) -------- 0.366 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to DebounceDown/SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 10 1.216 OSC.OSC to R5C3D.CLK Clock14MHz -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to DebounceDown/SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 10 1.216 OSC.OSC to R5C3D.CLK Clock14MHz -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.380ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DebounceUp/Counter_50__i1 (from Clock14MHz +) Destination: FF Data in DebounceUp/Counter_50__i1 (to Clock14MHz +) Delay: 0.367ns (63.8% logic, 36.2% route), 2 logic levels. Constraint Details: 0.367ns physical path delay DebounceUp/SLICE_6 to DebounceUp/SLICE_6 meets -0.013ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.013ns) by 0.380ns Physical Path Details: Data path DebounceUp/SLICE_6 to DebounceUp/SLICE_6: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R4C5A.CLK to R4C5A.Q1 DebounceUp/SLICE_6 (from Clock14MHz) ROUTE 4 0.133 R4C5A.Q1 to R4C5A.A1 DebounceUp/Counter_1 CTOF_DEL --- 0.101 R4C5A.A1 to R4C5A.F1 DebounceUp/SLICE_6 ROUTE 1 0.000 R4C5A.F1 to R4C5A.DI1 DebounceUp/n24 (to Clock14MHz) -------- 0.367 (63.8% logic, 36.2% route), 2 logic levels. Clock Skew Details: Source Clock Path OSCH_inst to DebounceUp/SLICE_6: Name Fanout Delay (ns) Site Resource ROUTE 10 1.216 OSC.OSC to R4C5A.CLK Clock14MHz -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path OSCH_inst to DebounceUp/SLICE_6: Name Fanout Delay (ns) Site Resource ROUTE 10 1.216 OSC.OSC to R4C5A.CLK Clock14MHz -------- 1.216 (0.0% logic, 100.0% route), 0 logic levels. Report Summary -------------- ---------------------------------------------------------------------------- Preference(MIN Delays) | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY NET "Clock14MHz" 14.000112 | | | MHz ; | 0.000 ns| 0.309 ns| 1 | | | ---------------------------------------------------------------------------- All preferences were met. Clock Domains Analysis ------------------------ Found 1 clocks: Clock Domain: Clock14MHz Source: OSCH_inst.OSC Loads: 10 Covered under: FREQUENCY NET "Clock14MHz" 14.000112 MHz ; Timing summary (Hold): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 78 paths, 1 nets, and 126 connections (96.92% coverage) Timing summary (Setup and Hold): --------------- Timing errors: 0 (setup), 0 (hold) Score: 0 (setup), 0 (hold) Cumulative negative slack: 0 (0+0) -------------------------------------------------------------------------------- --------------------------------------------------------------------------------