Lattice Synthesis Timing Report
--------------------------------------------------------------------------------
Lattice Synthesis Timing Report, Version  
Sat Jan 14 16:31:17 2023

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
------------------
Design:     top
Constraint file: top_temp_lse.sdc 
Report level:    verbose report, limited to 3 items per constraint
--------------------------------------------------------------------------------



================================================================================
Constraint: create_clock -period 5.000000 -name clk500 [get_nets \top_reveal_coretop_instance/jtck[0]]
            975 items scored, 975 timing errors detected.
--------------------------------------------------------------------------------


Error:  The following path violates requirements by 9.645ns

 Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)

   Source:         FD1P3DX    CK             \top_reveal_coretop_instance/pierwszyanalizator_inst_0/jtag_int_u/shift_reg__i17  (from \top_reveal_coretop_instance/jtck[0] +)
   Destination:    FD1P3BX    D              \top_reveal_coretop_instance/pierwszyanalizator_inst_0/jtag_int_u/tm_crc_i0_i0  (to \top_reveal_coretop_instance/jtck[0] +)

   Delay:                  14.485ns  (30.1% logic, 69.9% route), 10 logic levels.

 Constraint Details:

     14.485ns data_path \top_reveal_coretop_instance/pierwszyanalizator_inst_0/jtag_int_u/shift_reg__i17 to \top_reveal_coretop_instance/pierwszyanalizator_inst_0/jtag_int_u/tm_crc_i0_i0 violates
      5.000ns delay constraint less
      0.160ns L_S requirement (totaling 4.840ns) by 9.645ns

 Path Details: \top_reveal_coretop_instance/pierwszyanalizator_inst_0/jtag_int_u/shift_reg__i17 to \top_reveal_coretop_instance/pierwszyanalizator_inst_0/jtag_int_u/tm_crc_i0_i0

   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
L_CO        ---     0.444             CK to Q              \top_reveal_coretop_instance/pierwszyanalizator_inst_0/jtag_int_u/shift_reg__i17 (from \top_reveal_coretop_instance/jtck[0])
Route        44   e 2.117                                  \top_reveal_coretop_instance/pierwszyanalizator_inst_0/addr[0]
LUT4        ---     0.493              B to Z              \top_reveal_coretop_instance/pierwszyanalizator_inst_0/jtag_int_u/i1_2_lut_rep_218
Route         2   e 1.141                                  \top_reveal_coretop_instance/pierwszyanalizator_inst_0/n9293
LUT4        ---     0.493              D to Z              \top_reveal_coretop_instance/pierwszyanalizator_inst_0/tm_u/i8131_4_lut
Route        10   e 1.604                                  n8603
LUT4        ---     0.493              C to Z              \top_reveal_coretop_instance/pierwszyanalizator_inst_0/jtag_int_u/i8132_3_lut
Route         1   e 0.941                                  \top_reveal_coretop_instance/pierwszyanalizator_inst_0/jtag_int_u/n8604
LUT4        ---     0.493              C to Z              \top_reveal_coretop_instance/pierwszyanalizator_inst_0/jtag_int_u/mux_1464_i1_3_lut_3_lut
Route         1   e 0.941                                  \top_reveal_coretop_instance/pierwszyanalizator_inst_0/rd_dout_trig[0]
LUT4        ---     0.493              C to Z              \top_reveal_coretop_instance/pierwszyanalizator_inst_0/tm_u/i8393_4_lut_4_lut
Route         1   e 0.020                                  \top_reveal_coretop_instance/pierwszyanalizator_inst_0/n4
MUXL5       ---     0.233           ALUT to Z              \top_reveal_coretop_instance/pierwszyanalizator_inst_0/jtag_int_u/i8133
Route         1   e 0.020                                  \top_reveal_coretop_instance/pierwszyanalizator_inst_0/jtag_int_u/jtdo_first_bit_N_332
MUXL5       ---     0.233             D0 to Z              \top_reveal_coretop_instance/pierwszyanalizator_inst_0/jtag_int_u/i8249
Route         3   e 1.258                                  \top_reveal_coretop_instance/jtdo_N_292
LUT4        ---     0.493              B to Z              \top_reveal_coretop_instance/i1_2_lut
Route         2   e 1.141                                  \top_reveal_coretop_instance/er2_tdo[0]
LUT4        ---     0.493              D to Z              \top_reveal_coretop_instance/pierwszyanalizator_inst_0/jtag_int_u/i4521_4_lut
Route         1   e 0.941                                  \top_reveal_coretop_instance/pierwszyanalizator_inst_0/jtag_int_u/tm_crc_15__N_196[0]
                  --------
                   14.485  (30.1% logic, 69.9% route), 10 logic levels.


Error:  The following path violates requirements by 9.426ns

 Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)

   Source:         FD1P3DX    CK             \top_reveal_coretop_instance/pierwszyanalizator_inst_0/jtag_int_u/shift_reg__i19  (from \top_reveal_coretop_instance/jtck[0] +)
   Destination:    FD1P3BX    D              \top_reveal_coretop_instance/pierwszyanalizator_inst_0/jtag_int_u/tm_crc_i0_i0  (to \top_reveal_coretop_instance/jtck[0] +)

   Delay:                  14.266ns  (30.6% logic, 69.4% route), 10 logic levels.

 Constraint Details:

     14.266ns data_path \top_reveal_coretop_instance/pierwszyanalizator_inst_0/jtag_int_u/shift_reg__i19 to \top_reveal_coretop_instance/pierwszyanalizator_inst_0/jtag_int_u/tm_crc_i0_i0 violates
      5.000ns delay constraint less
      0.160ns L_S requirement (totaling 4.840ns) by 9.426ns

 Path Details: \top_reveal_coretop_instance/pierwszyanalizator_inst_0/jtag_int_u/shift_reg__i19 to \top_reveal_coretop_instance/pierwszyanalizator_inst_0/jtag_int_u/tm_crc_i0_i0

   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
L_CO        ---     0.444             CK to Q              \top_reveal_coretop_instance/pierwszyanalizator_inst_0/jtag_int_u/shift_reg__i19 (from \top_reveal_coretop_instance/jtck[0])
Route        25   e 1.898                                  \top_reveal_coretop_instance/pierwszyanalizator_inst_0/addr[2]
LUT4        ---     0.493              A to Z              \top_reveal_coretop_instance/pierwszyanalizator_inst_0/jtag_int_u/i1_2_lut_rep_218
Route         2   e 1.141                                  \top_reveal_coretop_instance/pierwszyanalizator_inst_0/n9293
LUT4        ---     0.493              D to Z              \top_reveal_coretop_instance/pierwszyanalizator_inst_0/tm_u/i8131_4_lut
Route        10   e 1.604                                  n8603
LUT4        ---     0.493              C to Z              \top_reveal_coretop_instance/pierwszyanalizator_inst_0/jtag_int_u/i8132_3_lut
Route         1   e 0.941                                  \top_reveal_coretop_instance/pierwszyanalizator_inst_0/jtag_int_u/n8604
LUT4        ---     0.493              C to Z              \top_reveal_coretop_instance/pierwszyanalizator_inst_0/jtag_int_u/mux_1464_i1_3_lut_3_lut
Route         1   e 0.941                                  \top_reveal_coretop_instance/pierwszyanalizator_inst_0/rd_dout_trig[0]
LUT4        ---     0.493              C to Z              \top_reveal_coretop_instance/pierwszyanalizator_inst_0/tm_u/i8393_4_lut_4_lut
Route         1   e 0.020                                  \top_reveal_coretop_instance/pierwszyanalizator_inst_0/n4
MUXL5       ---     0.233           ALUT to Z              \top_reveal_coretop_instance/pierwszyanalizator_inst_0/jtag_int_u/i8133
Route         1   e 0.020                                  \top_reveal_coretop_instance/pierwszyanalizator_inst_0/jtag_int_u/jtdo_first_bit_N_332
MUXL5       ---     0.233             D0 to Z              \top_reveal_coretop_instance/pierwszyanalizator_inst_0/jtag_int_u/i8249
Route         3   e 1.258                                  \top_reveal_coretop_instance/jtdo_N_292
LUT4        ---     0.493              B to Z              \top_reveal_coretop_instance/i1_2_lut
Route         2   e 1.141                                  \top_reveal_coretop_instance/er2_tdo[0]
LUT4        ---     0.493              D to Z              \top_reveal_coretop_instance/pierwszyanalizator_inst_0/jtag_int_u/i4521_4_lut
Route         1   e 0.941                                  \top_reveal_coretop_instance/pierwszyanalizator_inst_0/jtag_int_u/tm_crc_15__N_196[0]
                  --------
                   14.266  (30.6% logic, 69.4% route), 10 logic levels.


Error:  The following path violates requirements by 9.393ns

 Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)

   Source:         FD1P3DX    CK             \top_reveal_coretop_instance/pierwszyanalizator_inst_0/jtag_int_u/shift_reg__i25  (from \top_reveal_coretop_instance/jtck[0] +)
   Destination:    FD1P3BX    D              \top_reveal_coretop_instance/pierwszyanalizator_inst_0/jtag_int_u/tm_crc_i0_i0  (to \top_reveal_coretop_instance/jtck[0] +)

   Delay:                  14.233ns  (30.6% logic, 69.4% route), 10 logic levels.

 Constraint Details:

     14.233ns data_path \top_reveal_coretop_instance/pierwszyanalizator_inst_0/jtag_int_u/shift_reg__i25 to \top_reveal_coretop_instance/pierwszyanalizator_inst_0/jtag_int_u/tm_crc_i0_i0 violates
      5.000ns delay constraint less
      0.160ns L_S requirement (totaling 4.840ns) by 9.393ns

 Path Details: \top_reveal_coretop_instance/pierwszyanalizator_inst_0/jtag_int_u/shift_reg__i25 to \top_reveal_coretop_instance/pierwszyanalizator_inst_0/jtag_int_u/tm_crc_i0_i0

   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
L_CO        ---     0.444             CK to Q              \top_reveal_coretop_instance/pierwszyanalizator_inst_0/jtag_int_u/shift_reg__i25 (from \top_reveal_coretop_instance/jtck[0])
Route        14   e 1.865                                  \top_reveal_coretop_instance/pierwszyanalizator_inst_0/addr[8]
LUT4        ---     0.493              A to Z              \top_reveal_coretop_instance/pierwszyanalizator_inst_0/tm_u/i1_3_lut_4_lut_adj_185
Route         2   e 1.141                                  \top_reveal_coretop_instance/pierwszyanalizator_inst_0/n7767
LUT4        ---     0.493              A to Z              \top_reveal_coretop_instance/pierwszyanalizator_inst_0/tm_u/i8131_4_lut
Route        10   e 1.604                                  n8603
LUT4        ---     0.493              C to Z              \top_reveal_coretop_instance/pierwszyanalizator_inst_0/jtag_int_u/i8132_3_lut
Route         1   e 0.941                                  \top_reveal_coretop_instance/pierwszyanalizator_inst_0/jtag_int_u/n8604
LUT4        ---     0.493              C to Z              \top_reveal_coretop_instance/pierwszyanalizator_inst_0/jtag_int_u/mux_1464_i1_3_lut_3_lut
Route         1   e 0.941                                  \top_reveal_coretop_instance/pierwszyanalizator_inst_0/rd_dout_trig[0]
LUT4        ---     0.493              C to Z              \top_reveal_coretop_instance/pierwszyanalizator_inst_0/tm_u/i8393_4_lut_4_lut
Route         1   e 0.020                                  \top_reveal_coretop_instance/pierwszyanalizator_inst_0/n4
MUXL5       ---     0.233           ALUT to Z              \top_reveal_coretop_instance/pierwszyanalizator_inst_0/jtag_int_u/i8133
Route         1   e 0.020                                  \top_reveal_coretop_instance/pierwszyanalizator_inst_0/jtag_int_u/jtdo_first_bit_N_332
MUXL5       ---     0.233             D0 to Z              \top_reveal_coretop_instance/pierwszyanalizator_inst_0/jtag_int_u/i8249
Route         3   e 1.258                                  \top_reveal_coretop_instance/jtdo_N_292
LUT4        ---     0.493              B to Z              \top_reveal_coretop_instance/i1_2_lut
Route         2   e 1.141                                  \top_reveal_coretop_instance/er2_tdo[0]
LUT4        ---     0.493              D to Z              \top_reveal_coretop_instance/pierwszyanalizator_inst_0/jtag_int_u/i4521_4_lut
Route         1   e 0.941                                  \top_reveal_coretop_instance/pierwszyanalizator_inst_0/jtag_int_u/tm_crc_15__N_196[0]
                  --------
                   14.233  (30.6% logic, 69.4% route), 10 logic levels.

Warning: 14.645 ns is the maximum delay for this constraint.



================================================================================
Constraint: create_clock -period 71.428001 -waveform { 0.000000 35.714001 } -name Zegar [ get_nets { Clock14MHz } ]
            592 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed:  The following path meets requirements by 61.825ns

 Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)

   Source:         FD1P3DX    CK             \top_reveal_coretop_instance/pierwszyanalizator_inst_0/tm_u/post_trig_cntr_i0_i1  (from Clock14MHz +)
   Destination:    FD1P3DX    SP             \top_reveal_coretop_instance/pierwszyanalizator_inst_0/tm_u/trig_cntr_757__i1  (to Clock14MHz +)

   Delay:                   9.318ns  (25.9% logic, 74.1% route), 5 logic levels.

 Constraint Details:

      9.318ns data_path \top_reveal_coretop_instance/pierwszyanalizator_inst_0/tm_u/post_trig_cntr_i0_i1 to \top_reveal_coretop_instance/pierwszyanalizator_inst_0/tm_u/trig_cntr_757__i1 meets
     71.428ns delay constraint less
      0.285ns LCE_S requirement (totaling 71.143ns) by 61.825ns

 Path Details: \top_reveal_coretop_instance/pierwszyanalizator_inst_0/tm_u/post_trig_cntr_i0_i1 to \top_reveal_coretop_instance/pierwszyanalizator_inst_0/tm_u/trig_cntr_757__i1

   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
L_CO        ---     0.444             CK to Q              \top_reveal_coretop_instance/pierwszyanalizator_inst_0/tm_u/post_trig_cntr_i0_i1 (from Clock14MHz)
Route         7   e 1.559                                  \top_reveal_coretop_instance/pierwszyanalizator_inst_0/tm_u/post_trig_cntr[1]
LUT4        ---     0.493              A to Z              \top_reveal_coretop_instance/pierwszyanalizator_inst_0/tm_u/i1_3_lut_adj_225
Route         3   e 1.258                                  \top_reveal_coretop_instance/pierwszyanalizator_inst_0/tm_u/n11_adj_1166
LUT4        ---     0.493              B to Z              \top_reveal_coretop_instance/pierwszyanalizator_inst_0/tm_u/i1_4_lut_adj_224
Route        10   e 1.604                                  n13_adj_1209
LUT4        ---     0.493              C to Z              \top_reveal_coretop_instance/pierwszyanalizator_inst_0/tm_u/i1_2_lut_rep_179_3_lut
Route         4   e 1.340                                  \top_reveal_coretop_instance/pierwszyanalizator_inst_0/tm_u/n9254
LUT4        ---     0.493              B to Z              \top_reveal_coretop_instance/pierwszyanalizator_inst_0/tm_u/i1_3_lut_4_lut_adj_180
Route         2   e 1.141                                  \top_reveal_coretop_instance/pierwszyanalizator_inst_0/tm_u/clk[0]_N_keep_enable_86
                  --------
                    9.318  (25.9% logic, 74.1% route), 5 logic levels.


Passed:  The following path meets requirements by 61.825ns

 Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)

   Source:         FD1P3DX    CK             \top_reveal_coretop_instance/pierwszyanalizator_inst_0/tm_u/post_trig_cntr_i0_i1  (from Clock14MHz +)
   Destination:    FD1P3DX    SP             \top_reveal_coretop_instance/pierwszyanalizator_inst_0/tm_u/trig_cntr_757__i0  (to Clock14MHz +)

   Delay:                   9.318ns  (25.9% logic, 74.1% route), 5 logic levels.

 Constraint Details:

      9.318ns data_path \top_reveal_coretop_instance/pierwszyanalizator_inst_0/tm_u/post_trig_cntr_i0_i1 to \top_reveal_coretop_instance/pierwszyanalizator_inst_0/tm_u/trig_cntr_757__i0 meets
     71.428ns delay constraint less
      0.285ns LCE_S requirement (totaling 71.143ns) by 61.825ns

 Path Details: \top_reveal_coretop_instance/pierwszyanalizator_inst_0/tm_u/post_trig_cntr_i0_i1 to \top_reveal_coretop_instance/pierwszyanalizator_inst_0/tm_u/trig_cntr_757__i0

   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
L_CO        ---     0.444             CK to Q              \top_reveal_coretop_instance/pierwszyanalizator_inst_0/tm_u/post_trig_cntr_i0_i1 (from Clock14MHz)
Route         7   e 1.559                                  \top_reveal_coretop_instance/pierwszyanalizator_inst_0/tm_u/post_trig_cntr[1]
LUT4        ---     0.493              A to Z              \top_reveal_coretop_instance/pierwszyanalizator_inst_0/tm_u/i1_3_lut_adj_225
Route         3   e 1.258                                  \top_reveal_coretop_instance/pierwszyanalizator_inst_0/tm_u/n11_adj_1166
LUT4        ---     0.493              B to Z              \top_reveal_coretop_instance/pierwszyanalizator_inst_0/tm_u/i1_4_lut_adj_224
Route        10   e 1.604                                  n13_adj_1209
LUT4        ---     0.493              C to Z              \top_reveal_coretop_instance/pierwszyanalizator_inst_0/tm_u/i1_2_lut_rep_179_3_lut
Route         4   e 1.340                                  \top_reveal_coretop_instance/pierwszyanalizator_inst_0/tm_u/n9254
LUT4        ---     0.493              B to Z              \top_reveal_coretop_instance/pierwszyanalizator_inst_0/tm_u/i1_3_lut_4_lut_adj_180
Route         2   e 1.141                                  \top_reveal_coretop_instance/pierwszyanalizator_inst_0/tm_u/clk[0]_N_keep_enable_86
                  --------
                    9.318  (25.9% logic, 74.1% route), 5 logic levels.


Passed:  The following path meets requirements by 61.869ns

 Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)

   Source:         FD1P3DX    CK             \top_reveal_coretop_instance/pierwszyanalizator_inst_0/tm_u/post_trig_cntr_i0_i2  (from Clock14MHz +)
   Destination:    FD1P3DX    SP             \top_reveal_coretop_instance/pierwszyanalizator_inst_0/tm_u/trig_cntr_757__i1  (to Clock14MHz +)

   Delay:                   9.274ns  (26.1% logic, 73.9% route), 5 logic levels.

 Constraint Details:

      9.274ns data_path \top_reveal_coretop_instance/pierwszyanalizator_inst_0/tm_u/post_trig_cntr_i0_i2 to \top_reveal_coretop_instance/pierwszyanalizator_inst_0/tm_u/trig_cntr_757__i1 meets
     71.428ns delay constraint less
      0.285ns LCE_S requirement (totaling 71.143ns) by 61.869ns

 Path Details: \top_reveal_coretop_instance/pierwszyanalizator_inst_0/tm_u/post_trig_cntr_i0_i2 to \top_reveal_coretop_instance/pierwszyanalizator_inst_0/tm_u/trig_cntr_757__i1

   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
L_CO        ---     0.444             CK to Q              \top_reveal_coretop_instance/pierwszyanalizator_inst_0/tm_u/post_trig_cntr_i0_i2 (from Clock14MHz)
Route         6   e 1.515                                  \top_reveal_coretop_instance/pierwszyanalizator_inst_0/tm_u/post_trig_cntr[2]
LUT4        ---     0.493              B to Z              \top_reveal_coretop_instance/pierwszyanalizator_inst_0/tm_u/i3_2_lut
Route         3   e 1.258                                  \top_reveal_coretop_instance/pierwszyanalizator_inst_0/tm_u/n10
LUT4        ---     0.493              A to Z              \top_reveal_coretop_instance/pierwszyanalizator_inst_0/tm_u/i1_4_lut_adj_224
Route        10   e 1.604                                  n13_adj_1209
LUT4        ---     0.493              C to Z              \top_reveal_coretop_instance/pierwszyanalizator_inst_0/tm_u/i1_2_lut_rep_179_3_lut
Route         4   e 1.340                                  \top_reveal_coretop_instance/pierwszyanalizator_inst_0/tm_u/n9254
LUT4        ---     0.493              B to Z              \top_reveal_coretop_instance/pierwszyanalizator_inst_0/tm_u/i1_3_lut_4_lut_adj_180
Route         2   e 1.141                                  \top_reveal_coretop_instance/pierwszyanalizator_inst_0/tm_u/clk[0]_N_keep_enable_86
                  --------
                    9.274  (26.1% logic, 73.9% route), 5 logic levels.

Report: 9.603 ns is the maximum delay for this constraint.


Timing Report Summary
--------------
--------------------------------------------------------------------------------
Constraint                              |   Constraint|       Actual|Levels
--------------------------------------------------------------------------------
                                        |             |             |
create_clock -period 5.000000 -name     |             |             |
clk500 [get_nets                        |             |             |
\top_reveal_coretop_instance/jtck[0]]   |     5.000 ns|    14.645 ns|    10 *
                                        |             |             |
create_clock -period 71.428001          |             |             |
-waveform { 0.000000 35.714001 } -name  |             |             |
Zegar [ get_nets { Clock14MHz } ]       |    71.428 ns|     9.603 ns|     5  
                                        |             |             |
--------------------------------------------------------------------------------


1 constraints not met.

--------------------------------------------------------------------------------
Critical Nets                           |   Loads|  Errors| % of total
--------------------------------------------------------------------------------
\top_reveal_coretop_instance/pierwszyana|        |        |
lizator_inst_0/tm_u/n2887               |       7|     410|     42.05%
                                        |        |        |
\top_reveal_coretop_instance/pierwszyana|        |        |
lizator_inst_0/wen_jtck                 |       3|     255|     26.15%
                                        |        |        |
\top_reveal_coretop_instance/n2804      |      17|     181|     18.56%
                                        |        |        |
\top_reveal_coretop_instance/pierwszyana|        |        |
lizator_inst_0/tm_u/n7145               |       1|     172|     17.64%
                                        |        |        |
\top_reveal_coretop_instance/pierwszyana|        |        |
lizator_inst_0/n224                     |       3|     155|     15.90%
                                        |        |        |
\top_reveal_coretop_instance/pierwszyana|        |        |
lizator_inst_0/tm_u/n7146               |       1|     138|     14.15%
                                        |        |        |
\top_reveal_coretop_instance/pierwszyana|        |        |
lizator_inst_0/jtag_int_u/n200          |       1|     128|     13.13%
                                        |        |        |
\top_reveal_coretop_instance/pierwszyana|        |        |
lizator_inst_0/trig_u/te_0/n31          |      21|     122|     12.51%
                                        |        |        |
\top_reveal_coretop_instance/pierwszyana|        |        |
lizator_inst_0/tm_u/n14                 |       1|     116|     11.90%
                                        |        |        |
\top_reveal_coretop_instance/jtck_N_90_e|        |        |
nable_61                                |      16|     112|     11.49%
                                        |        |        |
\top_reveal_coretop_instance/pierwszyana|        |        |
lizator_inst_0/jtag_int_u/n9265         |       4|     112|     11.49%
                                        |        |        |
\top_reveal_coretop_instance/pierwszyana|        |        |
lizator_inst_0/trig_u/te_0/n8313        |       1|     108|     11.08%
                                        |        |        |
jshift_d1                               |      29|     108|     11.08%
                                        |        |        |
\top_reveal_coretop_instance/pierwszyana|        |        |
lizator_inst_0/tm_u/n7144               |       1|     102|     10.46%
                                        |        |        |
\top_reveal_coretop_instance/pierwszyana|        |        |
lizator_inst_0/jtag_int_u/n9303         |       5|      99|     10.15%
                                        |        |        |
\top_reveal_coretop_instance/pierwszyana|        |        |
lizator_inst_0/n7879                    |       9|      99|     10.15%
                                        |        |        |
n8603                                   |      10|      98|     10.05%
                                        |        |        |
--------------------------------------------------------------------------------


Timing summary:
---------------

Timing errors: 975  Score: 4678276

Constraints cover  5081 paths, 883 nets, and 2482 connections (73.5% coverage)


Peak memory: 72024064 bytes, TRCE: 2453504 bytes, DLYMAN: 327680 bytes
CPU_TIME_REPORT: 0 secs