--------------------------------------------------------------------------------
Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
Wed Jan 11 16:38:15 2023

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
------------------
Design file:     top
Device,speed:    LCMXO2-1200HC,4
Report level:    verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------


Derating parameters
-------------------
Voltage:    3.300 V



================================================================================
Preference: FREQUENCY 10.000000 MHz ;
            0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed:  The following path meets requirements by 97.500ns
         The internal maximum frequency of the following component is 400.000 MHz

 Logical Details:  Cell type  Pin name       Component name

   Destination:    SLICE      CLK            SLICE_10

   Delay:               2.500ns -- based on Minimum Pulse Width

Report:  400.000MHz is the maximum frequency for this preference.


================================================================================
Preference: FREQUENCY NET "Clock14MHz" 20.000000 MHz ;
            10 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
 

Passed: The following path meets requirements by 45.378ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              DebounceUp/FilteredSignal_17  (from Clock14MHz +)
   Destination:    FF         Data in        Counter0/Value_i3  (to Clock14MHz +)

   Delay:               4.456ns  (43.5% logic, 56.5% route), 4 logic levels.

 Constraint Details:

      4.456ns physical path delay SLICE_1 to SLICE_3 meets
     50.000ns delay constraint less
      0.000ns skew and
      0.166ns DIN_SET requirement (totaling 49.834ns) by 45.378ns

 Physical Path Details:

      Data path SLICE_1 to SLICE_3:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.452      R4C5B.CLK to       R4C5B.Q0 SLICE_1 (from Clock14MHz)
ROUTE         5     1.032       R4C5B.Q0 to R4C5B.B1       ButtonUpFiltered
CTOF_DEL    ---     0.495       R4C5B.B1 to       R4C5B.F1 SLICE_1
ROUTE         4     1.042       R4C5B.F1 to R4C3B.B1       n412
CTOF_DEL    ---     0.495       R4C3B.B1 to       R4C3B.F1 SLICE_10
ROUTE         2     0.445       R4C3B.F1 to R4C3D.C1       n4
CTOF_DEL    ---     0.495       R4C3D.C1 to       R4C3D.F1 SLICE_3
ROUTE         1     0.000       R4C3D.F1 to R4C3D.DI1      Counter0/Value_3_N_23_3 (to Clock14MHz)
                  --------
                    4.456   (43.5% logic, 56.5% route), 4 logic levels.

 Clock Skew Details: 

      Source Clock Path OSCH_inst to SLICE_1:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        10     3.541        OSC.OSC to R4C5B.CLK      Clock14MHz
                  --------
                    3.541   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path OSCH_inst to SLICE_3:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        10     3.541        OSC.OSC to R4C3D.CLK      Clock14MHz
                  --------
                    3.541   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 45.417ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              UpDetector/Previous_13  (from Clock14MHz +)
   Destination:    FF         Data in        Counter0/Value_i3  (to Clock14MHz +)

   Delay:               4.417ns  (43.9% logic, 56.1% route), 4 logic levels.

 Constraint Details:

      4.417ns physical path delay SLICE_9 to SLICE_3 meets
     50.000ns delay constraint less
      0.000ns skew and
      0.166ns DIN_SET requirement (totaling 49.834ns) by 45.417ns

 Physical Path Details:

      Data path SLICE_9 to SLICE_3:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.452      R4C3C.CLK to       R4C3C.Q0 SLICE_9 (from Clock14MHz)
ROUTE         2     0.993       R4C3C.Q0 to R4C5B.A1       UpDetector/Previous
CTOF_DEL    ---     0.495       R4C5B.A1 to       R4C5B.F1 SLICE_1
ROUTE         4     1.042       R4C5B.F1 to R4C3B.B1       n412
CTOF_DEL    ---     0.495       R4C3B.B1 to       R4C3B.F1 SLICE_10
ROUTE         2     0.445       R4C3B.F1 to R4C3D.C1       n4
CTOF_DEL    ---     0.495       R4C3D.C1 to       R4C3D.F1 SLICE_3
ROUTE         1     0.000       R4C3D.F1 to R4C3D.DI1      Counter0/Value_3_N_23_3 (to Clock14MHz)
                  --------
                    4.417   (43.9% logic, 56.1% route), 4 logic levels.

 Clock Skew Details: 

      Source Clock Path OSCH_inst to SLICE_9:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        10     3.541        OSC.OSC to R4C3C.CLK      Clock14MHz
                  --------
                    3.541   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path OSCH_inst to SLICE_3:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        10     3.541        OSC.OSC to R4C3D.CLK      Clock14MHz
                  --------
                    3.541   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 45.499ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              DebounceUp/FilteredSignal_17  (from Clock14MHz +)
   Destination:    FF         Data in        Counter0/Value_i2  (to Clock14MHz +)

   Delay:               4.335ns  (44.7% logic, 55.3% route), 4 logic levels.

 Constraint Details:

      4.335ns physical path delay SLICE_1 to SLICE_3 meets
     50.000ns delay constraint less
      0.000ns skew and
      0.166ns DIN_SET requirement (totaling 49.834ns) by 45.499ns

 Physical Path Details:

      Data path SLICE_1 to SLICE_3:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.452      R4C5B.CLK to       R4C5B.Q0 SLICE_1 (from Clock14MHz)
ROUTE         5     1.032       R4C5B.Q0 to R4C5B.B1       ButtonUpFiltered
CTOF_DEL    ---     0.495       R4C5B.B1 to       R4C5B.F1 SLICE_1
ROUTE         4     1.042       R4C5B.F1 to R4C3B.B1       n412
CTOF_DEL    ---     0.495       R4C3B.B1 to       R4C3B.F1 SLICE_10
ROUTE         2     0.324       R4C3B.F1 to R4C3D.D0       n4
CTOF_DEL    ---     0.495       R4C3D.D0 to       R4C3D.F0 SLICE_3
ROUTE         1     0.000       R4C3D.F0 to R4C3D.DI0      Value_3_N_23_2 (to Clock14MHz)
                  --------
                    4.335   (44.7% logic, 55.3% route), 4 logic levels.

 Clock Skew Details: 

      Source Clock Path OSCH_inst to SLICE_1:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        10     3.541        OSC.OSC to R4C5B.CLK      Clock14MHz
                  --------
                    3.541   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path OSCH_inst to SLICE_3:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        10     3.541        OSC.OSC to R4C3D.CLK      Clock14MHz
                  --------
                    3.541   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 45.538ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              UpDetector/Previous_13  (from Clock14MHz +)
   Destination:    FF         Data in        Counter0/Value_i2  (to Clock14MHz +)

   Delay:               4.296ns  (45.1% logic, 54.9% route), 4 logic levels.

 Constraint Details:

      4.296ns physical path delay SLICE_9 to SLICE_3 meets
     50.000ns delay constraint less
      0.000ns skew and
      0.166ns DIN_SET requirement (totaling 49.834ns) by 45.538ns

 Physical Path Details:

      Data path SLICE_9 to SLICE_3:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.452      R4C3C.CLK to       R4C3C.Q0 SLICE_9 (from Clock14MHz)
ROUTE         2     0.993       R4C3C.Q0 to R4C5B.A1       UpDetector/Previous
CTOF_DEL    ---     0.495       R4C5B.A1 to       R4C5B.F1 SLICE_1
ROUTE         4     1.042       R4C5B.F1 to R4C3B.B1       n412
CTOF_DEL    ---     0.495       R4C3B.B1 to       R4C3B.F1 SLICE_10
ROUTE         2     0.324       R4C3B.F1 to R4C3D.D0       n4
CTOF_DEL    ---     0.495       R4C3D.D0 to       R4C3D.F0 SLICE_3
ROUTE         1     0.000       R4C3D.F0 to R4C3D.DI0      Value_3_N_23_2 (to Clock14MHz)
                  --------
                    4.296   (45.1% logic, 54.9% route), 4 logic levels.

 Clock Skew Details: 

      Source Clock Path OSCH_inst to SLICE_9:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        10     3.541        OSC.OSC to R4C3C.CLK      Clock14MHz
                  --------
                    3.541   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path OSCH_inst to SLICE_3:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        10     3.541        OSC.OSC to R4C3D.CLK      Clock14MHz
                  --------
                    3.541   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 45.594ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              DebounceDown/Counter_52__i3  (from Clock14MHz +)
   Destination:    FF         Data in        DebounceDown/Counter_52__i1  (to Clock14MHz +)
                   FF                        DebounceDown/Counter_52__i0

   Delay:               4.132ns  (34.9% logic, 65.1% route), 3 logic levels.

 Constraint Details:

      4.132ns physical path delay DebounceDown/SLICE_5 to DebounceDown/SLICE_4 meets
     50.000ns delay constraint less
      0.000ns skew and
      0.274ns LSR_SET requirement (totaling 49.726ns) by 45.594ns

 Physical Path Details:

      Data path DebounceDown/SLICE_5 to DebounceDown/SLICE_4:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.452      R5C3D.CLK to       R5C3D.Q1 DebounceDown/SLICE_5 (from Clock14MHz)
ROUTE         2     0.974       R5C3D.Q1 to R5C3B.A1       DebounceDown/Counter_3
CTOF_DEL    ---     0.495       R5C3B.A1 to       R5C3B.F1 SLICE_0
ROUTE         2     0.632       R5C3B.F1 to R4C3C.D1       n203
CTOF_DEL    ---     0.495       R4C3C.D1 to       R4C3C.F1 SLICE_9
ROUTE         2     1.084       R4C3C.F1 to R5C3A.LSR      DebounceDown/n189 (to Clock14MHz)
                  --------
                    4.132   (34.9% logic, 65.1% route), 3 logic levels.

 Clock Skew Details: 

      Source Clock Path OSCH_inst to DebounceDown/SLICE_5:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        10     3.541        OSC.OSC to R5C3D.CLK      Clock14MHz
                  --------
                    3.541   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path OSCH_inst to DebounceDown/SLICE_4:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        10     3.541        OSC.OSC to R5C3A.CLK      Clock14MHz
                  --------
                    3.541   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 45.594ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              DebounceDown/Counter_52__i3  (from Clock14MHz +)
   Destination:    FF         Data in        DebounceDown/Counter_52__i3  (to Clock14MHz +)
                   FF                        DebounceDown/Counter_52__i2

   Delay:               4.132ns  (34.9% logic, 65.1% route), 3 logic levels.

 Constraint Details:

      4.132ns physical path delay DebounceDown/SLICE_5 to DebounceDown/SLICE_5 meets
     50.000ns delay constraint less
      0.000ns skew and
      0.274ns LSR_SET requirement (totaling 49.726ns) by 45.594ns

 Physical Path Details:

      Data path DebounceDown/SLICE_5 to DebounceDown/SLICE_5:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.452      R5C3D.CLK to       R5C3D.Q1 DebounceDown/SLICE_5 (from Clock14MHz)
ROUTE         2     0.974       R5C3D.Q1 to R5C3B.A1       DebounceDown/Counter_3
CTOF_DEL    ---     0.495       R5C3B.A1 to       R5C3B.F1 SLICE_0
ROUTE         2     0.632       R5C3B.F1 to R4C3C.D1       n203
CTOF_DEL    ---     0.495       R4C3C.D1 to       R4C3C.F1 SLICE_9
ROUTE         2     1.084       R4C3C.F1 to R5C3D.LSR      DebounceDown/n189 (to Clock14MHz)
                  --------
                    4.132   (34.9% logic, 65.1% route), 3 logic levels.

 Clock Skew Details: 

      Source Clock Path OSCH_inst to DebounceDown/SLICE_5:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        10     3.541        OSC.OSC to R5C3D.CLK      Clock14MHz
                  --------
                    3.541   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path OSCH_inst to DebounceDown/SLICE_5:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        10     3.541        OSC.OSC to R5C3D.CLK      Clock14MHz
                  --------
                    3.541   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 45.802ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              DebounceDown/Counter_52__i1  (from Clock14MHz +)
   Destination:    FF         Data in        DebounceDown/Counter_52__i1  (to Clock14MHz +)
                   FF                        DebounceDown/Counter_52__i0

   Delay:               3.924ns  (36.7% logic, 63.3% route), 3 logic levels.

 Constraint Details:

      3.924ns physical path delay DebounceDown/SLICE_4 to DebounceDown/SLICE_4 meets
     50.000ns delay constraint less
      0.000ns skew and
      0.274ns LSR_SET requirement (totaling 49.726ns) by 45.802ns

 Physical Path Details:

      Data path DebounceDown/SLICE_4 to DebounceDown/SLICE_4:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.452      R5C3A.CLK to       R5C3A.Q1 DebounceDown/SLICE_4 (from Clock14MHz)
ROUTE         4     0.766       R5C3A.Q1 to R5C3B.C1       DebounceDown/Counter_1
CTOF_DEL    ---     0.495       R5C3B.C1 to       R5C3B.F1 SLICE_0
ROUTE         2     0.632       R5C3B.F1 to R4C3C.D1       n203
CTOF_DEL    ---     0.495       R4C3C.D1 to       R4C3C.F1 SLICE_9
ROUTE         2     1.084       R4C3C.F1 to R5C3A.LSR      DebounceDown/n189 (to Clock14MHz)
                  --------
                    3.924   (36.7% logic, 63.3% route), 3 logic levels.

 Clock Skew Details: 

      Source Clock Path OSCH_inst to DebounceDown/SLICE_4:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        10     3.541        OSC.OSC to R5C3A.CLK      Clock14MHz
                  --------
                    3.541   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path OSCH_inst to DebounceDown/SLICE_4:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        10     3.541        OSC.OSC to R5C3A.CLK      Clock14MHz
                  --------
                    3.541   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 45.802ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              DebounceDown/Counter_52__i1  (from Clock14MHz +)
   Destination:    FF         Data in        DebounceDown/Counter_52__i3  (to Clock14MHz +)
                   FF                        DebounceDown/Counter_52__i2

   Delay:               3.924ns  (36.7% logic, 63.3% route), 3 logic levels.

 Constraint Details:

      3.924ns physical path delay DebounceDown/SLICE_4 to DebounceDown/SLICE_5 meets
     50.000ns delay constraint less
      0.000ns skew and
      0.274ns LSR_SET requirement (totaling 49.726ns) by 45.802ns

 Physical Path Details:

      Data path DebounceDown/SLICE_4 to DebounceDown/SLICE_5:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.452      R5C3A.CLK to       R5C3A.Q1 DebounceDown/SLICE_4 (from Clock14MHz)
ROUTE         4     0.766       R5C3A.Q1 to R5C3B.C1       DebounceDown/Counter_1
CTOF_DEL    ---     0.495       R5C3B.C1 to       R5C3B.F1 SLICE_0
ROUTE         2     0.632       R5C3B.F1 to R4C3C.D1       n203
CTOF_DEL    ---     0.495       R4C3C.D1 to       R4C3C.F1 SLICE_9
ROUTE         2     1.084       R4C3C.F1 to R5C3D.LSR      DebounceDown/n189 (to Clock14MHz)
                  --------
                    3.924   (36.7% logic, 63.3% route), 3 logic levels.

 Clock Skew Details: 

      Source Clock Path OSCH_inst to DebounceDown/SLICE_4:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        10     3.541        OSC.OSC to R5C3A.CLK      Clock14MHz
                  --------
                    3.541   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path OSCH_inst to DebounceDown/SLICE_5:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        10     3.541        OSC.OSC to R5C3D.CLK      Clock14MHz
                  --------
                    3.541   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 45.920ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              DebounceDown/Counter_52__i2  (from Clock14MHz +)
   Destination:    FF         Data in        DebounceDown/Counter_52__i1  (to Clock14MHz +)
                   FF                        DebounceDown/Counter_52__i0

   Delay:               3.806ns  (37.9% logic, 62.1% route), 3 logic levels.

 Constraint Details:

      3.806ns physical path delay DebounceDown/SLICE_5 to DebounceDown/SLICE_4 meets
     50.000ns delay constraint less
      0.000ns skew and
      0.274ns LSR_SET requirement (totaling 49.726ns) by 45.920ns

 Physical Path Details:

      Data path DebounceDown/SLICE_5 to DebounceDown/SLICE_4:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.452      R5C3D.CLK to       R5C3D.Q0 DebounceDown/SLICE_5 (from Clock14MHz)
ROUTE         3     0.648       R5C3D.Q0 to R5C3B.D1       DebounceDown/Counter_2
CTOF_DEL    ---     0.495       R5C3B.D1 to       R5C3B.F1 SLICE_0
ROUTE         2     0.632       R5C3B.F1 to R4C3C.D1       n203
CTOF_DEL    ---     0.495       R4C3C.D1 to       R4C3C.F1 SLICE_9
ROUTE         2     1.084       R4C3C.F1 to R5C3A.LSR      DebounceDown/n189 (to Clock14MHz)
                  --------
                    3.806   (37.9% logic, 62.1% route), 3 logic levels.

 Clock Skew Details: 

      Source Clock Path OSCH_inst to DebounceDown/SLICE_5:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        10     3.541        OSC.OSC to R5C3D.CLK      Clock14MHz
                  --------
                    3.541   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path OSCH_inst to DebounceDown/SLICE_4:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        10     3.541        OSC.OSC to R5C3A.CLK      Clock14MHz
                  --------
                    3.541   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 45.920ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              DebounceDown/Counter_52__i2  (from Clock14MHz +)
   Destination:    FF         Data in        DebounceDown/Counter_52__i3  (to Clock14MHz +)
                   FF                        DebounceDown/Counter_52__i2

   Delay:               3.806ns  (37.9% logic, 62.1% route), 3 logic levels.

 Constraint Details:

      3.806ns physical path delay DebounceDown/SLICE_5 to DebounceDown/SLICE_5 meets
     50.000ns delay constraint less
      0.000ns skew and
      0.274ns LSR_SET requirement (totaling 49.726ns) by 45.920ns

 Physical Path Details:

      Data path DebounceDown/SLICE_5 to DebounceDown/SLICE_5:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.452      R5C3D.CLK to       R5C3D.Q0 DebounceDown/SLICE_5 (from Clock14MHz)
ROUTE         3     0.648       R5C3D.Q0 to R5C3B.D1       DebounceDown/Counter_2
CTOF_DEL    ---     0.495       R5C3B.D1 to       R5C3B.F1 SLICE_0
ROUTE         2     0.632       R5C3B.F1 to R4C3C.D1       n203
CTOF_DEL    ---     0.495       R4C3C.D1 to       R4C3C.F1 SLICE_9
ROUTE         2     1.084       R4C3C.F1 to R5C3D.LSR      DebounceDown/n189 (to Clock14MHz)
                  --------
                    3.806   (37.9% logic, 62.1% route), 3 logic levels.

 Clock Skew Details: 

      Source Clock Path OSCH_inst to DebounceDown/SLICE_5:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        10     3.541        OSC.OSC to R5C3D.CLK      Clock14MHz
                  --------
                    3.541   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path OSCH_inst to DebounceDown/SLICE_5:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE        10     3.541        OSC.OSC to R5C3D.CLK      Clock14MHz
                  --------
                    3.541   (0.0% logic, 100.0% route), 0 logic levels.

Report:  216.357MHz is the maximum frequency for this preference.

Report Summary
--------------
----------------------------------------------------------------------------
Preference                              |   Constraint|       Actual|Levels
----------------------------------------------------------------------------
                                        |             |             |
FREQUENCY 10.000000 MHz ;               |   10.000 MHz|  400.000 MHz|   0  
                                        |             |             |
FREQUENCY NET "Clock14MHz" 20.000000    |             |             |
MHz ;                                   |   20.000 MHz|  216.357 MHz|   4  
                                        |             |             |
----------------------------------------------------------------------------


All preferences were met.


Clock Domains Analysis
------------------------

Found 1 clocks:

Clock Domain: Clock14MHz   Source: OSCH_inst.OSC   Loads: 10
   Covered under: FREQUENCY NET "Clock14MHz" 20.000000 MHz ;


Timing summary (Setup):
---------------

Timing errors: 0  Score: 0
Cumulative negative slack: 0

Constraints cover 78 paths, 1 nets, and 126 connections (96.92% coverage)